TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 682

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

SPxCLK Period (Master)
SPxCLK Period (Slave)
SPxCLK rise up time
SPxCLK fall down time
Master mode: SPxCLK low level pulse width
Master mode: SPxCLK high level pulse width
Master Mode:
Master Mode:
Master Mode:
Master Mode:
Master Mode:
Slave mode:
Slave mode:
Slave mode:
Slave mode:
Slave mode:
Slave mode: SPxCLK low level pulse width
Slave mode: SPxCLK high level pulse width
SPxCLK rise/fall to output data valid
SPxCLK rise/fall to output data hold
SPxCLK rise/fall to input data valid delay time
SPxCLK rise/fall to input data hold
SPxFSS valid to SPxCLK rise/fall
SPxCLK rise/fall to output data valid delay time
SPxCLK rise/fall to output data hold
SPxCLK rise/fall to input data hold
SPxFSS valid to SPxCLK rise/fall
SPxCLK rise/fall to input data valid delay time
AC measurement conditions
(
27.6.4 SPP Controllor (SSP)
Note
The letter ”T” used in the equation in the table represents the period of internal bus ｆrequency(fpcLK)
Output level: High=0.7×DVDD5, Low =0.3×DVDD5
Input level: High=0.9×DVDD5, Low =0.1×DVDD5
Load capacitance CL = 30 pF
Ta = -45 to 85℃
(Note) Baud rate Clcok is set under below condition
)The “Equation” column in the table shows the specifications under the conditions DVDD5 = 4.0 to 5.5 V.
Parameter
Master mode
Slave mode
m = (<CPSDVSR> × (1+<SCR>)) = f
n = f
<CPSDVR> is set only even number and “m” must set during 65204
sys
／ SPxCLK (65024
Symbol
TMPM380/M382 - 9 / 21 -
t
t
t
t
t
t
t
t
t
t
t
ODSM
ODHM
t
t
t
ODSS
ODHS
OFSM
WHM
IDSM
IDHM
OFSS
WLM
WHS
IDSS
IDHS
WLS
T
T
t
t
m
r
f
s
However more
(m)T / 2 - 20.0
(m)T / 2 –20.0
(n)T /2 ＋ (2T)
(n)T / 2 –10.0
(n)T / 2 –10.0
than、100nS
(m)T/2 -15
(m)T -15
(3T) +15
≧
(n)T -20
(m)T
35.0
Min
(n)T
5.0
10
n
≧
Equation
12 )
sys
／ SPxCLK
(3T) + 35
(m)T+15
Max
15.0
15.0
15.0
(3.3MHz)
85 – 115
(10MHz)
40MHz
≥
(m=4
n=12)
fsys
15.0
15.0
15.0
35.0
35.0
100
300
145
145
110
200
280
5.0
30
30
10
90
m
TMPM380/M382
≥
2
Unit
nS