TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 380

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

SC0MOD2
13.4.6 Mode control register 2
<TBEMP>:
<RBFLL>:
<TXRUN>:
<SBLEN>:
<DRCHG>:
<WBUF>:
<SWRST1:0>:
bit Symbol
Read/Write
After reset
Function
This flag shows that the transmit double buffers are empty. When data in the transmit
double buffers is moved to the transmit shift register and the double buffers are empty,
this bit is set to “1.” Writing data again to the double buffers sets this bit to “0.”
If double buffering is disabled, this flag is insignificant.
This is a flag to show that the receive double buffers are full. When a receive operation
is completed and received data is moved from the receive shift register to the receive
double buffers, this bit changes to “1” while reading this bit changes it to “0.”
If double buffering is disabled, this flag is insignificant.
This is a status flag to show that data transmission is in progress.
<TXRUN> and <TBEMP> bits indicate the following status.
This specifies the length of stop bit transmission in the UART mode. On the receive
side, the decision is made using only a single bit regardless of the <SBLEN> setting.
Specifies the direction of data transfer in the I/O interface mode. In the UART mode, it is
fixed to LSB first.
This parameter enables or disables the transmit/receive buffers to transmit (in both
SCLK output/input modes) and receive (in SCLK output mode) data in the I/O interface
mode and to transmit data in the UART. When receiving data in the I/O interface mode (I
SCLK input) and UART mode, double buffering is enabled in both cases that 0 or 1 is
set to <WBUF> bit.
Transmit
buffer
empty flag
0: full
1: Empty
<TXRUN>
Overwriting “01” in place of “10” generates a software reset. When this software reset
is executed, the following bits, transmitter, reciever and FIFO are initialized (see note
1, 2 and 3).
TBEMP
SC0MOD0
SC0MOD1
SC0MOD2
7
1
1
0
Register
SC0CR
Receive
Buffer full
flag
0: Empty
1: full
RBFLL
<TBEMP>
6
R
0
1
0
-
RXE
TXE
TBEMP,RBFLL,TXRUN,
OERR,PERR,FERR
TMPM380/M382 - 31 / 52 -
In
transmission
flag
0: Stop
1: Start
TXRUN
5
0
Transmission in progress
Wait state with data in TX buffer
Transmission completed
Bit
STOP bit
(for UART)
0: 1-bit
1: 2-bit
SBLEN
4
0
Setting
transfer
direction
0: LSB first
1: MSB first
DRCHG
3
0
Status
W-buffer
0: Disabled
1: Enabled
WBUF
R/W
2
0
SOFT RESET
Overwrite “01” on “10”to
reset.
SWRST1
TMPM380/M382
1
0
SWRST0
0
0