TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 454

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

INTSBIn interrupt request
SCL
SDA
<PIN>
INTSBIn interrupt
request
SCL
SDA
<PIN>
9
Receiver mode (<TRX> = “0”)
If the next data to be transmitted has eight bits, the transmit data is written into SBInDBR. If
the data has different length, <BC2:0> and <ACK> are programmed and the received data
is read from SBInDBR to release the SCL line.
transmission of a slave address is undefined.) On reading the data, <PIN> is set to “1,” and
the serial clock is output to the SCL pin to transfer the next data word. In the last bit, when
the acknowledgment signal becomes the “L” level, “0” is output to the SDA pin.
After that, the INTSBIn interrupt request is generated, and <PIN> is cleared to “0,” pulling
the SCL pin to the “L” level. Each time the received data is read from SBInDBR, one-word
transfer clock and an acknowledgement signal are output.
immediately before reading the data word second to last. This disables generation of an
acknowledgment clock for the last data word. When the transfer is completed, an interrupt
request is generated. After the interrupt processing, <BC2:0> must be set to “001” and the
data must be read so that a clock is generated for 1-bit transfer. At this time, the master
receiver holds the SDA bus line at the “H” level, which signals the end of transfer to the
transmitter as an acknowledgment signal.
In the interrupt processing for terminating the reception of 1-bit data, the stop condition is
generated to terminate the data transfer.
Fig 15-17 Terminating Data Transmission in the Master Receiver Mode
To terminate the data transmission from the transmitter, <ACK> must be set to “0”
Fig 15-16 <BC2:0> = “000” and <ACK> = “1” (Receiver Mode)
D7
Read out the received data after clearing <ACK> to "0”.
1
D7
Read the received data
1
D6
2
D6
2
TMPM380/M382 - 25 / 41 -
D5
3
D5
3
D4
4
D4
4
D3
5
D3
5
D2
6
D2
6
(The data read immediately after
D1
7
D1
7
D0
8
D0
8
Master output
Slave output
TMPM380/M382
ACK
Master output
Slave output
1
Read out the received
data after setting
<BC2:0> to "001."
9
Acknowledgment signal
to transmitter “H”
Acknowledgment
signal from receiver
Next D7