TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 498

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

17.3 Control Registers
17.3.1 Watchdog Timer Mode Register (WDMOD)
17.3.2 Watchdog Timer Control Register (WDCR)
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
1. Enabling/disabling the watchdog timer <WDTE>
2. Specifying the detection time of the watchdog timer <WDTP2: 0>
3. Enabling/disabling the watchdog timer in IDLE mode <I2WDT>
•
•
Enabling/disabling the watchdog timer in IDLE mode is controlled by this bit. Writing “1” to this bit
enables the watchdog timer and writing “0” to this bit disables the watchdog timer in IDLE mode.
When resetting, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled.
To disable the watchdog timer, this bit must be set to "0" and, at the same time, the disable code
(0xB1) must be written to the WDCR register. This dual setting is intended to minimize the
probability that the watchdog timer may inadvertently be disabled if a runaway occurs.
To change the status of the watchdog timer from "disable" to "enable," set the <WDTE> bit to "1".
This is a 3-bit register for specifying the INTWDT time for runaway detection. When a reset is
effected, this register is initialized to WDMOD <WDTP2: 0> = "000." Fig 17-4 shows the detection
time of the watchdog timer.
Setting this bit to "1" enables the watch dog timer to be reset when a runaway is detected. Since a
reset initializes this bit to "1," a counter overflow causes a reset.
This is a register for disabling the watchdog timer function and controlling the clearing function of
the binary counter.
By writing the disable code (0xB1) to this WDCR register after setting WDMOD <WDTE> to "0," the
watchdog timer can be disabled.
Set WDMOD <WDTE> to "1".
Disabling control
Enabling control
4.
(Note) Watchdog timer is stopped in stop mode.
Watchdog timer out reset connection <RESCR>
WDMOD
WDCR
← 0
← 1 0 1 1 0 0 0 1
− − − − − − −
TMPM380/M382 - 3 / 6 -
Clears WDTE to "0."
Writes the disable code (0xB1).
TMPM380/M382