XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 327

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

20.4.4.3 PWM Initialization
MC68HC908AZ60A — Rev 2.0
MOTOROLA
NOTE:
NOTE:
status and control register (TBSC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O
pin.
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
1. In the TIMB status and control register (TBSC):
2. In the TIMB counter modulo registers (TBMODH–TBMODL) write
3. In the TIMB channel x registers (TBCHxH–TBCHxL) write the
4. In TIMB channel x status and control register (TBSCx):
the value for the required PWM period.
value for the required pulse width.
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter and prescaler by setting the TIMB
a. Write 0:1 (for unbuffered output compare or PWM signals) or
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
Timer Interface Module B (TIMB)
reset bit, TRST.
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB–MSxA (see
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level (see
Timer Interface Module B (TIMB)
Table
Table
Functional Description
20-2).
Technical Data
20-2).
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