XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 509

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

27.6.5.2 Receiving a Message in Block Mode
27.6.5.3 Transmitting a Message in Block Mode
27.6.5.4 J1850 Bus Errors
MC68HC908AZ60A — Rev 2.0
MOTOROLA
Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All of the other features of
the frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR register until the message is complete.
The programmer should wait until the TDRE flag (see
Vector
register. The BDLC does not contain any predefined maximum J1850
message length requirement.
The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
Transmission Error
CRC Error
If the message transmitted by the BDLC contains invalid bits or
framing symbols on non-byte boundaries, this constitutes a
transmission error. When a transmission error is detected, the BDLC
immediately will cease transmitting. The error condition ($1C) is
reflected in the BSVR register (see
bit (IE in BCR1) is set, a CPU interrupt request from the BDLC is
generated.
A cyclical redundancy check (CRC) error is detected when the data
bytes and CRC byte of a received message are processed and the
CRC calculation result is not equal to $C4. The CRC code will detect
Register) is set prior to writing a new byte of data into the BDR
Byte Data Link Controller (BDLC)
Table
Byte Data Link Controller (BDLC)
27-6). If the interrupt enable
BDLC Protocol Handler
BDLC State
Technical Data
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