XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 347

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

21.7 PIT During Break Interrupts
21.8 I/O Registers
21.8.1 PIT Status and Control Register
MC68HC908AZ60A — Rev 2.0
MOTOROLA
A break interrupt stops the PIT counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see
on page 168).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
The following I/O registers control and monitor operation of the PIT:
The PIT status and control register:
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PIT status and control register (PSC)
PIT counter registers (PCNTH–PCNTL)
PIT counter modulo registers (PMODH–PMODL)
Enables PIT interrupt
Flags PIT overflows
Stops the PIT counter
Programmable Interrupt Timer (PIT)
SIM Break Flag Control Register
Programmable Interrupt Timer (PIT)
PIT During Break Interrupts
Technical Data
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