XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 364

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Input/Output Ports
22.6.2 Data Direction Register D
Technical Data
364
NOTE:
Address:
DDRD bits always determine whether reading port D returns the states
of the latches or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 22-13
Reset:
Read:
Write:
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA.
The PTD4/ATD12/TBCLK pin is the external clock input for the TIMB.
The prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK or
PTD4/ATD12/TBCLK as the TIM clock input. (See
Status and Control Registers
Status and Control Registers
the TIM clock, PTD6/ATD14/TACLK
available for general-purpose I/O. While TACLK/TBCLK are selected
corresponding DDRD bits have no effect.
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
$0007
Bit 7
Figure 22-12. Data Direction Register D (DDRD)
0
shows the port D I/O logic.
DDRD6
Input/Output Ports
6
0
DDRD5
5
0
DDRD4
4
0
on page 336). When not selected as
on page 462 and
and
DDRD3
3
0
PTD4/ATD12/TBCLK are
MC68HC908AZ60A — Rev 2.0
DDRD2
2
0
TIMB Channel
TIMA Channel
DDRD1
1
0
MOTOROLA
DDRD0
Bit 0
0