XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 485

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

27.4 Functional Description
MC68HC908AZ60A — Rev 2.0
MOTOROLA
NOTE:
Figure 27-1
interface contains the software addressable registers and provides the
link between the CPU and the buffers. The buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The
protocol handler is responsible for the encoding and decoding of data
bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section
and the analog physical interface. The wave shaping, driving, and
digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the
SAE Standard J1850 Class B Data Communication Network Interface
specification.
It is recommended that the reader be familiar with the SAE J1850
document and ISO Serial Communication document prior to proceeding
with this section of the MC68HC908AZ60A specification.
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Block mode receive and transmit supported
Supports 4X receive mode, 41.6 kbps
Digital loopback mode
Analog loopback mode
In-frame response (IFR) types 0, 1, 2, and 3 supported
Byte Data Link Controller (BDLC)
shows the organization of the BDLC module. The CPU
Byte Data Link Controller (BDLC)
Functional Description
Technical Data
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