XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 491

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

27.5.1.1 Operation
MC68HC908AZ60A — Rev 2.0
MOTOROLA
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRxD)
MUX INTERFACE
CLOCK
D
Figure 27-4. BDLC Rx Digital Filter Block Diagram
INPUT
SYNC
The clock for the digital filter is provided by the MUX interface clock (see
f
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can only be decremented from this state.
Alternatively, should the counter eventually reach the value 0, the digital
filter decides that the condition of the BDRxD signal is at a stable logic
level 0 and the data latch is reset, causing the filtered Rx data signal to
become a logic level 0. Furthermore, the counter is prevented from
underflowing and can only be incremented from this state.
BDLC
Q
parameter in
Byte Data Link Controller (BDLC)
UP/DOWN
4-BIT UP/DOWN COUTER
Table
27-4). At each positive edge of the clock
OUT
Byte Data Link Controller (BDLC)
D
LATCH
DATA
Q
BDLC MUX Interface
RX DATA OUT
FILTERED
Technical Data
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