MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 24

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

MT90225/226
Data Sheet
2.2 The ATM Transmission Convergence
The Transmit Convergence (TC) function integrates the circuitry to support ATM cell payload scrambling, HEC
generation and the generation of Idle cells for use with the T1/E1/J1 or DSL trunks. Each of the available ATM TC
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circuits can use the polynomial X
+ 1 to scramble the ATM cell payload field. The MT90225/226 ATM cell payload
scrambling function can be disabled.
8
2
The ITU I.432 polynomial X
+ X
+ X + 1 is used to generate the HEC field of the ATM cell. By default, the ATM
6
4
2
Forum polynomial X
+ X
+ X
+ 1 is added to the calculated HEC octet. The addition of the ATM Forum polynomial
can be disabled. The resulting calculation is then written on the HEC field and the ATM cell is ready for transmission
over the flexible TDM Interface.
In cases where the TC block requests a cell to be transferred to any of the serial interfaces and the TX Link UTOPIA
FIFO has no cell ready for transmission, then the TC block will automatically send an IDLE cell to the line. The
default values for the Idle cells comply with the ATM Forum Specification and are pre-loaded in the MT90225/226
following a reset. The TX Cell RAM Control (0x0080) register can be used to re-initialize the TX Cell RAM. The
content of the Idle cell is pre-initialized with the header bytes set at 0x00, 0x00, 0x00 and 0x01. The payload bytes
are set to 0x6A.
Idle Cells are transmitted on the TC serial Interface until the bit corresponding to the link in the UTOPIA Input
Link PHY Enable (0x0050) register is set. Then, the ATM User cells are transferred from the Input UTOPIA
port to the TX serial port.
2.2.1 TX Cell RAM and TX Link FIFO Length
The internal TX Cell RAM can hold up to 119 cells. A one cell space for predefined Idle Cell is reserved for
MT90225/226 operation.
The remaining 118 cells can be assigned to any of the 16/8 TX Link UTOPIA FIFOs. The MT90225/226 implements
one TX Link UTOPIA FIFO for each link. Each TX Link UTOPIA FIFO is associated with one TX UTOPIA PHY
Address. Please refer to section 5.0 "UTOPIA Interface Operation" for more details.
ATM cells received from the ATM port are placed in a TX LINK UTOPIA FIFO, waiting to be transmitted. If the
Idle/Unassigned cell removal option is selected, these cells are dropped. If the TX LINK UTOPIA FIFO is empty, an
Idle cell is sent to the output link.
TX Link FIFO Length Definition Register (0x008B - 0x0092) are used to set the size of the TX Link UTOPIA
FIFO. A maximum of 15 cells can be assigned to any single FIFO. The size of unused TX Link UTOPIA FIFOs should
be set to zero.
2.3 Parallel to Serial TDM Interface
ATM cell octet byte alignment conforms to ITU G.804 recommendations for T1 or E1 framer parallel to serial format
conversion.
The TDM TX Link Control Register (0x0600-0x060F) and TDM RX Link Control Register (0x0700-0x070F)
registers are used to select the serial mode of operation. Additionally, the serial links can operate at rates up to
2.5Mb/s individually, or up to 5.0Mb/s when paired or 10Mb/s when grouped in fours. Refer to Description of the
TDM interface in Section 4.0 for more details.
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Zarlink Semiconductor Inc.