MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 42

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

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6.2.2 IRQ Link Status and IRQ Link Enable Registers
There are sixteen IRQ Link Status (0x0435-0x0444) and sixteen IRQ Link Enable (0x0445-0x0454) registers; one
of each per link. The following types of interrupts are reported (in the least significant bits of the IRQ Link Status
registers) for each link:
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Bit 0 (LSB) is a status bit. It reports an interrupt for an overflow condition in one or more of the 24 counters associated
with the link. It is also used to report an overflow condition in the UTOPIA RX FIFO associated with a TDM link in
TC mode. If enabled, a counter generates an interrupt request when it overflows (i.e starts over from 0 after reaching
the maximum counter value). See Section 6.1 Counter Block for more details on the operation of the counters. These
13 sources of overflow can be identified through the IRQ Link FIFO Overflow and IRQ UTOPIA FIFO Overflow
status registers.
Reading the IRQ Link Status (0x0435-0x0444) register does not clear the source of interrupt. The bit 0 status is
reset by any one of the following procedures:
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Bits 1 to 6 and 9 to 11 of the IRQ Link Status (0x0435-0x0444) registers are latches that report the source of an
interrupt. Writing a ’0’ these bits will reset the status bit (will reset the latch). Writing ’0’ to bit 0 has no effect on the
status bit.
Writing a ’1’ has no effect on the bits 0 to 6 and 9 to 11 of the IRQ Link Status (0x0435-0x0444) register.
Each one of these 10 interrupt sources can be enabled by writing a ’1’ in the IRQ Link Enable (0x0445-0x0454)
registers to the bit corresponding to the interrupt source.
In some situations, an interrupt source can be masked as part of an interrupt service routine. This makes it possible
to detect further interrupts of higher priority. For example, if an interrupt for a counter is received, the source of the
interrupt can be masked by writing 0 to the corresponding bit and then starting a separate process outside of the
Interrupt Service Routine. The independent process would read, reload and re-enable the counter to produce
another interrupt service request, if necessary. At the end of this process, the enable bit in the IRQ Link Enable
(0x0445-0x0454) register would be set to ’1’ to detect any future interrupt requests.
6.2.3 IRQ Link TC Overflow Status Registers
The IRQ Link TC Overflow Status Registers (0x0410 - 0x041F) report the overflow condition from any of the
counters associated with the TX TDM link, the RX TDM link or the TX UTOPIA I/F. They also report the overflow
condition from the level of the UTOPIA RX FIFO. The 10 interrupt sources are organized as follows:
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Bit 9 latched: reports the end of an LCD (Loss of Cell Delineation) condition on a RX TDM link.
Bit 1 latched: reports an LCD (Loss of Cell Delineation) condition on a RX TDM link.
disabling (masking) the IRQ for this specific counter
clearing the overflow status bit in the IRQ Link TC Overflow Status (0x0410-0x041F) registers
disabling the interrupt in the IRQ Link TC Overflow Enable (0x0434) or in the corresponding Link Counter
registers.
1 bit (12) for the RX UTOPIA FIFO overflow
4 bits (11:8) for the UTOPIA Input counters
2 bits (7,5) for the TX TDM Link counters
3 bits (3:1) for the RX TDM Link counters
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