MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 62

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

62
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
6:5
4:3
10
11
9
8
7
2
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
Unused. Read 0’s.
Reserved. Write 0 for normal operation.
Automatic ATM cell synchronization
When 1: Bit mode cell delineation is performed. To be used when no RXSYNC signal is
provided. Register 0x0741 must also be initialized.
When 0: Byte mode cell delineation is performed. Must be used when a valid RXSYNC
signal is provided.
Reserved. Write 0 for normal operation.
Digital Loopback mode
When 1, loopback mode, RXCK, RXSYNC and DSTi come from the TX pins of the same
link. Both TX and RX blocks operate normally.
When 0, normal mode, RXCK, RXSYNC and DSTi come from the RX pins of the link
Link enable:
0: RX Port is not active
1: RX port is active
Data rate:
11: 8.192 Mb/sec.
10: 4.096 Mb/sec.
01: 2.048 Mb/sec
00: 1.544 Mb/sec
Multiplex mode select:
00: no demultiplexing,
01: demultiplex on a per byte basis, 1 link to 2 links. Valid only for ST-BUS mode.
10: demultiplex on a per byte basis, 1 link to 4 links. Valid only for ST-BUS mode.
Clock and sync format:
When 0, TDM is in Generic mode: clock is 1x data rate and sync is 1 bit long at beginning
of frame.
When 1, TDM is ST-BUS Format: clock 2x data rate and sync as per ST-BUS format
Clock polarity:
When 0, the data is sampled at the rising edge of RXCK.
When 1, the data is sampled at the falling edge of RXCK.
This bit is ignored in ST-BUS Format.
Sync polarity:
When 0, the sync pulse is active low.
When 1, the sync pulse is active high.
This bit is ignored in ST-BUS Format.
0x0700 - 0x070F (16 reg)
1 reg. per RX link
0000
Table 41 - TDM RX Link Control Register
Zarlink Semiconductor Inc.
Description
Data Sheet