MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 41
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MT90225AG
Manufacturer Part Number
MT90225AG
Description
Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90225AG.pdf
(88 pages)
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Data Sheet
6.2 Interrupt Block
The MT90225/226 can generate interrupts from many sources. All interrupt sources can be enabled or disabled.
Write action is required to clear the source of interrupt. Interrupts are grouped on a per link basis, with six
sub-categories for each link. These special interrupts are only present in the Link 0 IRQ Status register. Refer to
Figure 14 for a representation of the interrupt register hierarchy.
6.2.1 IRQ Master Status and IRQ Master Enable Registers
There is a IRQ Master Status (0x0455) register that reports interrupts generated by any event on any of the links.
Each bit of this register corresponds to a link. A ’1’ in a bit position indicates that the associated link is reporting an
interrupt condition. For each bit in the IRQ Master Status (0x0455) register, there is a corresponding bit in the IRQ
Master Enable (0x0433) register. When any IRQ source is active and the corresponding Enable bit is ’1’, then the
IRQ pin will go LOW (active).
The IRQ Master Status (0x0455) register always reports the current state of the source(s) of interrupt. It does not
latch the interrupt request(s); it only reports that one or more bit(s) in one or more IRQ Link Status register(s) is
(are) set.
The bits that are read as active (’1’ value) are cleared when the source of the interrupt is cleared or when the
corresponding bit(s) in the IRQ Link Enable (0x0445-0x0454) register(s) is (are) set to 0. Writing to or reading from
the IRQ Master Status (0x0455) register has no effect on the level of the interrupt pin.
RX FIFO Overflow
4 UTOPIA
Counters
1 UTOPIA
Counters
Counters
Link Overflow Status
3 RX
2 TX
Figure 14 - IRQ Register Hierarchy
Link 15
End of LCD
Link 14
S
T
A
T
U
S
Zarlink Semiconductor Inc.
Link 13
.......
LCD
Link 3
Registers
16 x IRQ
Link 2
Link
1
9
0
Link 1
S
T
A
T
U
S
Link 0
E
N
A
B
E
L
Link 15
Link 0
Registers
1 x IRQ
Master
S
T
A
T
U
S
E
N
A
B
E
L
IRQ PIN
41
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