MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 60
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MT90225AG
Manufacturer Part Number
MT90225AG
Description
Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90225AG.pdf
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Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
15:0
15
14
15
14
...
...
1
0
1
0
Type
Type
Type
R/W
R
R
R
R
R
R
R
R
R
R
When 1: TXCK faulty on link 15.
When 1: TXCK faulty on link 14.
....
When 1: TXCK faulty on link 1.
When 1: TXCK faulty on link 0.
When 1: RXCK faulty on link 15.
When 1: RXCK faulty on link 14.
....
When 1: RXCK faulty on link 1.
When 1: RXCK faulty on link 0.
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTo pin is in High Z mode for the corresponding time slot.
This registers controls time slots 31:16. For T1 links, bit 8 (timeslot 24) must be zero.
0x0630 (1 reg)
1 reg. for all 16 TXCK signals
0000
0x0631 (1 reg)
1 reg. for all 16 RXCK signals
0000
0x0620 - 0x062F (16 reg)
Control time slot 31:16
0000
Table 35 - TDM TX Mapping (timeslots 31:16) Register
Table 37 - RXCK Status Register
Table 36 - TXCK Status Register
Zarlink Semiconductor Inc.
Description
Description
Description
Data Sheet
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