MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 3

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
1.0 Device Architecture ......................................................................................................... 22
2.0 The ATM Transmit Path................................................................................................... 22
3.0 The ATM Receive Path .................................................................................................... 25
4.0 Description of the TDM Interface.................................................................................... 27
5.0 UTOPIA Interface Operation ........................................................................................... 36
6.0 Support Blocks ................................................................................................................ 39
1.1 MT90225/6 Main Functions ...................................................................................................................... 22
2.1 Cell In Control ........................................................................................................................................... 23
2.2 The ATM Transmission Convergence ...................................................................................................... 24
2.3 Parallel to Serial TDM Interface ................................................................................................................ 24
3.1 Cell Delineation Function .......................................................................................................................... 25
3.2 De-Scrambling and ATM Cell Filtering...................................................................................................... 27
4.1 Single mode .............................................................................................................................................. 27
4.2 Wire-OR mode .......................................................................................................................................... 30
4.3 Multiplex mode .......................................................................................................................................... 31
4.4 Non-framed mode ..................................................................................................................................... 32
4.5 Clock formats ............................................................................................................................................ 33
4.6 TDM Loopback Mode................................................................................................................................ 33
4.7 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters................................................................. 34
4.8 Clocking Options ....................................................................................................................................... 34
5.1 ATM Input Port.......................................................................................................................................... 36
5.2 ATM Output Port ....................................................................................................................................... 37
5.3 UTOPIA Operation .................................................................................................................................... 37
5.4 UTOPIA Operation With a Single PHY ..................................................................................................... 37
5.5 UTOPIA Operation with Multiple PHY....................................................................................................... 38
5.6 UTOPIA Loopback .................................................................................................................................... 38
5.7 Examples of UTOPIA Operation Modes ................................................................................................... 38
6.1 Counter Block ........................................................................................................................................... 39
6.2 Interrupt Block ........................................................................................................................................... 41
2.2.1 TX Cell RAM and TX Link FIFO Length .......................................................................................... 24
3.1.1 Cell Delineation with Sync signal..................................................................................................... 27
3.1.2 Cell Delineation without Sync signal................................................................................................ 27
4.1.1 Single mode - Generic 1.544MHz ................................................................................................... 28
4.1.2 Single mode - Generic 2.048MHz ................................................................................................... 28
4.1.3 Single mode -ST-BUS ..................................................................................................................... 29
4.2.1 Wire-OR mode - 2 link grouping ...................................................................................................... 30
4.2.2 Wire-OR mode - 4 link grouping ...................................................................................................... 30
4.3.1 Multiplex mode - 2 link multiplexing................................................................................................. 31
4.3.2 Multiplex mode - 4 link multiplexing................................................................................................. 31
4.4.1 Non-framed mode - 2.5Mbps........................................................................................................... 32
4.4.2 Non-framed mode - 5.0Mbps........................................................................................................... 32
4.4.3 Non-framed mode - 10.0Mbps......................................................................................................... 33
4.8.1 Verification of the RXSYNC Period ................................................................................................. 35
4.8.2 Verification of the TXSYNC Period.................................................................................................. 35
4.8.3 Primary and Secondary Reference Signals..................................................................................... 35
4.8.4 Verification of Clock Activity ............................................................................................................ 35
4.8.5 Clock Selection................................................................................................................................ 36
6.1.1 UTOPIA Input I/F counters .............................................................................................................. 39
6.1.2 Transmit TDM I/F Counters ............................................................................................................. 40
6.1.3 Receive TDM I/F Counters .............................................................................................................. 40
6.1.4 Access to the Counters ................................................................................................................... 40
6.1.5 Latching counter mode .................................................................................................................... 40
Zarlink Semiconductor Inc.
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