MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 5

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

MT90225/226
Data Sheet
List of Figures
Figure 1 - MT90225/226 Functional Block Diagram ................................................................................................1
Figure 2 - MT90226 Pinout (Bottom View) ..............................................................................................................9
Figure 3 - MT90225 Pinout (Bottom View) ........................................................................................................... 10
Figure 4 - MT90225/226 Functional Block Diagram -Transmitter ........................................................................ 23
Figure 5 - Example of TC Mode Operation (Using Four of Sixteen Possible UTOPIA-Output Ports) .................. 25
Figure 6 - Cell Delineation State Diagram ............................................................................................................ 25
Figure 7 - SYNC State Block Diagram ................................................................................................................. 26
Figure 8 - Single mode - Generic 1.544 MHz ....................................................................................................... 28
Figure 9 - Single mode - Generic 2.048 MHz ....................................................................................................... 29
Figure 10 - Single mode - ST-BUS....................................................................................................................... 29
Figure 11 - TXCK and TXSYNC Output Pin Source Options ............................................................................... 35
Figure 12 - ATM Interface to MT90225/226 ......................................................................................................... 38
Figure 13 - ATM Interface to Multiple MT90225/226 ............................................................................................ 39
Figure 14 - IRQ Register Hierarchy ...................................................................................................................... 41
Figure 15 - MT90225 interfacing MT9076 ST-BUS mode with all links synchronous. ......................................... 64
Figure 16 - MT90225 interfacing MT9076 ST-BUS mode with asynchronous links. ............................................ 65
Figure 17 - MT90225 interfacing MT9076 Generic mode with asynchronous links. ............................................ 66
Figure 18 - MT90225 interfacing MT9072 ............................................................................................................ 67
Figure 19 - Setup and Hold Time Definition ......................................................................................................... 72
Figure 20 - Tri-State Timing ................................................................................................................................. 72
Figure 21 - Output Delay Timing .......................................................................................................................... 72
Figure 22 - CPU Interface Motorola Timing - Read Access ................................................................................. 74
Figure 23 - CPU Interface Intel Timing - Read Access ........................................................................................ 75
Figure 24 - CPU Interface Motorola Timing - Write Access ................................................................................. 76
Figure 25 - CPU Interface Intel Timing - Write Access......................................................................................... 77
Figure 26 - ST-BUS Timing .................................................................................................................................. 79
Figure 27 - Generic Bus Timing ........................................................................................................................... 80
Figure 28 - JTAG Port Timing .............................................................................................................................. 81
Figure 29 - System Clock and Reset.................................................................................................................... 82
Zarlink Semiconductor Inc.
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