MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 40

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

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6.1.2 Transmit TDM I/F Counters
There are two counters associated with the each of the sixteen transmit TDM links for a total of 32 Transmit counters.
These counters record the following information:
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6.1.3 Receive TDM I/F Counters
There are three counters associated with each of the sixteen receive TDM links for a total of 48 receive counters.
These counters record the following information and are active as soon as the RX TDM port is enabled:
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6.1.4 Access to the Counters
Accessing (READ) counters is a three step operation. First, the desired counter must be selected by writing to the
Select Counter Register (0x0432). Second, the READ command (’0x00x101’) is written to the Counter Transfer
Command (0x040F) register. This command causes the current three byte count value to be copied from the
specified counter to the two 16 bit-wide Counter Byte 3 Register (0x0430) and Counter Bytes 2 and 1 Register
(0x0431) registers (note that this value is unchanged until another counter read command is issued). And third, the
Counter Byte 3 Register (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers are read to obtain
the three byte count value of the selected counter.
Pre-loading (WRITE) a counter is also a three step function. First, the three byte pre-load value is written to the two
16 bit-wide Counter Byte 3 Register (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers.
Second, the identification of the counter to be pre-loaded is written to the Select Counter Register (0x0432). And
third, the WRITE command (’0x00x001’) is written to the Counter Transfer Command (0x040F) register.
The IRQ enable bit of a counter is set, or reset, by selecting the counter and writing to the appropriate bit of the
Counter Transfer Command (0x040F) register. The value’0x001010’ enables the counter IRQ and ’xxx00010’
disables (masks) it.
6.1.5 Latching counter mode
An additional mode of operation is available in the counter block where the values of all the counters are transferred,
all at the same time, to a series of internal registers. The transfer can be initiated automatically based on an input
signal or following a transfer command under software control.
When the source for the latch command is from the dedicated input pin, the user has the option to use directly this
signal as a latch command or to divide the incoming signal by 8000 before generating the latch command (for
example, using the 8 kHz F0 frame pulse signal to create 1 second intervals). Bits in the Counter Transfer
Command (0x040F) register are defined to support these features.
The counters are 24 bits wide when operated without the latching option and are 16 bits wide when the latching
feature is enabled. After each latch signal, the counters are reset to 0 in order to report the number of events
between two latch commands.
Before the latching mode is enabled, the counters may be loaded (or reset), but the software should not write to the
counters after the latching mode is enabled.
the total number of cells sent through the TDM link
the total number of Idle cells or the total number of user cells sent through the TDM link
the total number of cells received through the TDM link.
the total number of Idle cells or the total number of user cells received through the TDM link
the total number of cells with wrong HEC, discarded or not, received through the TDM link but not including
the cells where the HEC is corrected
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