MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 37

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
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5.2 ATM Output Port
The MT90225/226 supports a 53 byte cell stream via the ATM output port. Cells received at the ATM output port
are stored in the RX UTOPIA FIFO before being processed by the UTOPIA Interface. The output of the UTOPIA
Interface can be stopped by the ATM Layer device by de-asserting the RxENB* signal.
The start of a cell is marked with the SOC signal, which is active during the transmission of the first byte of a cell.
The following 52 bytes are expected to belong to the same cell.
The RX byte clock (RxClk) can be up to 52 MHz and is checked against the system clock. If the incoming byte clock
frequency is lower than 1/128 of the system clock, bit 3 of the General Status (0x040E) register will be set. This bit
is cleared by overwriting it with 0. This aids in debugging as the presence of a UTOPIA clock is required not only for
data transfer but also for proper operation of the UTOPIA registers.
Overflow conditions in the RX UTOPIA FIFO associated with any of the 16 PHY RX Addresses cause a status bit
to be set in either the IRQ Link TC Overflow Status (0x0410-0x041F). These status bits are cleared by overwriting
them with 0. Additionally, for each status bit there is an Interrupt Enable bit in the associated IRQ Link TC Overflow
Enable (0x0434) register. When enabled, the status bit is reported in an Interrupt register. See section 6.2 Interrupt
Block for more details.
The size of the RX UTOPIA FIFO is fixed at four cells for each of the PHY Addresses.
Note that in the receive direction, the parity bit that is generated is not valid if the receive Utopia clock is faster than
50 MHz.
5.3 UTOPIA Operation
Each Utopia port inside an MT90225/226 corresponds to a physical serial TDM (T1, E1, J1, DSL) line. Up to sixteen
PHY ports can be supported by one MT90225. Up to eight MT90225/226s can be connected to a UTOPIA bus. The
ports in the same device represent only one electrical load on the UTOPIA bus. The MT90225/226 supports the full
UTOPIA L2 Interface limit of 31 PHY addresses.
The MPHY address at the input port of MT90225/226 (TxAddr[4:0]) is used to store the cell in one specific TX
UTOPIA FIFO.
The MPHY address at the output port (RxAddr[4:0]) is used to retrieve the cells from the proper RX UTOPIA FIFO.
5.4 UTOPIA Operation With a Single PHY
A single ATM layer device with a UTOPIA L2 MPHY port can be connected to the ATM input port of one
MT90225/226. Another ATM-Layer device using the UTOPIA L2 MPHY input interface is used to receive ATM cells
from the MT90225/226.
The address pins should be set to the value programmed by the management interface.
The ’01’ option is used to verify the HEC of an incoming cell. If the HEC value is wrong and if it can be
corrected (1 bit error), then the cell is corrected and accepted as a good cell. The bad HEC counter is not
incremented if the HEC is corrected. The bad HEC counter is incremented if the HEC value cannot be
corrected. In this mode, the cell is always accepted. The MT90225/226 will re-generate a valid HEC based
on the content of the 4-byte header that was received.
The ’10’ option is used to verify the HEC on the incoming cell and discard the cell if the HEC value is wrong.
The bad HEC counter is incremented if a cell is discarded.
The ’11’ option is similar to mode ’01’ except that if the HEC value cannot be corrected, then the cell is
discarded. If the HEC value is corrected, the bad HEC counter is not incremented.
Zarlink Semiconductor Inc.
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