MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 35

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Data Sheet
4.8.1 Verification of the RXSYNC Period
The RXSYNC signal is used to align the incoming DSTi data to retrieve all the T1 or E1 channels. The RXSYNC
pulse can be present for each TDM frame (8Khz) or once per Superframe (an integer number of frames, typically
12 or 16). The period and position of the RXSYNC is verified for each receive block independently. A status bit (1
per link) in the RXSYNC Status (0x0730) register is set if the synchronization pulse occurs at an unexpected time
in the frame. The RX block will be re-aligned with this new synchronization pulse.
4.8.2 Verification of the TXSYNC Period
The TXSYNC signal is used to align the outgoing DSTo data to retrieve all the T1 or E1 channels. When defined as
input, the TXSYNC pulse can be present for each TDM frame (8Khz) or once per Superframe (every 12 or 24 TDM
frames). The period and position of the TXSYNC is verified for each transmit block independently. A status bit (1
per link) in the TXSYNC Status (0x0633) register is set if the synchronization pulse occurs at an unexpected time
in the frame. The TX block will be re-aligned with this new synchronization pulse.
4.8.3 Primary and Secondary Reference Signals
Two output pins are provided to simplify the external circuitry required when using an external PLL. These two pins,
PLLREF0 and PLLREF1, re-route any of the RXCK signals and drive the primary and secondary reference signals
of a PLL under software control. Refer to Section 8, Application Notes, for examples.
4.8.4 Verification of Clock Activity
The MT90225/226 implements circuitry to determine whether or not a selected clock signal is active. This feature is
used to ensure a clock is operational before using it as a source for one or more transmit links. A read of the TXCK
Status (0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) register indicates a faulty clock if a bit is ’1’.
A value of ’0’ for these bits means that activity was observed on this clock. This circuitry does not measure the
frequency of a clock signal, it only detects activity on the TXCK, RXCK and REFCK signals.
Figure 11 - TXCK and TXSYNC Output Pin Source Options
RXCK 0-15
REFCK 0-3
RXCK 0-15
TX Cell FIFO
Cell Delineation
Zarlink Semiconductor Inc.
P/S
S/P
PLLREF1
PLLREF0
DSTi
RXCK
RXSYNC
TXSYNC
DSTo
TXCK
35