MT90225AG Zarlink Semiconductor, MT90225AG Datasheet - Page 34

• Manufacturer Part Number: MT90225AG
• Description: Description = 16 Port TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

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Besides TDM loopacks, there is also a UTOPIA loopback described in the section 5.7.
4.7 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters
Each serial TDM link has assigned S/P and P/S units. The P/S unit takes a byte from the cell RAM and converts it
to a serial bit stream. The S/P unit takes a byte from the DSTi input and converts it to parallel format for use by the
Cell Delineation block.
P/S and S/P units can be set-up differently on a per port and per direction basis (i.e. the transmit and receive function
of the same port can use different configurations). The following features are supported:
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When the TXCK and TXSYNC signals are outputs, the source for the TXCLK is software selectable from any of the
RXCK inputs or any of the four external REFCKs. The TXSYNC signal is generated from the TXCK and is
independent from (not aligned with) the RXSYNC or other TXSYNC signals.
4.8 Clocking Options
TXCK and TXSYNC can be either input or output signals. When TXCK and TXSYNC are inputs, they are generated
by external circuitry. When TXCK and TXSYNC are outputs, TXCK source is software selectable and can be any of
the RXCK signals or four external REFCK inputs (see Figure 11). The TXSYNC is generated from the TXCK signal.
The RXCK pins are always defined as inputs and the proper signal must be provided to each input.
programming links as T1 or E1
using ST-BUS and Generic TDM modes
enabling/disabling the P/S and S/P units (if they are disabled the associated outputs are Tri-stated)
selecting TDM timeslots as per mapping registers.
independently programming the polarity of RXCK, TXCK, RXSYNC and TXSYNC signals (Generic TDM
mode only)
generating/accepting TXSYNC and TXCLK signals to support most T1 and E1 framers (depending on the
programmed mode)
monitoring RXSYNC signal period and reporting the unexpected occurrence of a synchronization signal
monitoring TXSYNC signal period (when defined as input) and reporting the unexpected occurrence of a
synchronization signal
generating a TXSYNC pulse on every TDM frame when defined as output
Zarlink Semiconductor Inc.
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