ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 119

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

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16.0 Analog to Digital Converter (ADC)
The ADC receives analog signals on eight channels (AD0-
7). It converts these signals to their digital representation
and stores the results in four byte-wide registers.
16.1 FEATURES
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•
•
•
•
•
•
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Analog
Power
3.3 V
5.0 V
or
8-bit resolution
8 input channels
Input voltage range from zero to V
Internal or external reference voltage
Timing specifications:
— 10 ADC-clock cycles conversion time
— Up to 1 MHz ADC clock
— Programmable sampling time to guarantee input
Flexible conversion modes:
— Single or continuous conversion
— Single channel or four channel scanning
Polling or interrupt driven operation
Zero current consumption when disabled, low current
when enabled
High impedance inputs
settling time
AV
V
V
CC
IN0
IN7
+
C
22
2
F
AD0
AD7
0.47
0.1
C
C
F
F
1
3
AV
AGND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
V
REF
CC
REF
Ref
Analog
Int
MUX
AV
to other
modules
AV
8:1
CC
Analog to Digital Converter (ADC)
CC
Figure 16-1. ADC Functional Diagram
Control Logic
and Hold
Sample
ADC
C
s
DAC
119
INTREF
16.2 FUNCTIONAL DESCRIPTION
The ADC has eight analog inputs, AD0-7, as shown in Fig-
ure 16-1. The analog multiplexer selects one of them and
connects it to Sample and Hold. The input signal is sampled
before the conversion begins.
Sample and Hold charges the C
pling time, and holds the voltage value on this capacitor dur-
ing the conversion period. Programmable sampling time
allows the voltage on the sampling capacitor to settle before
being latched.
The ADC is implemented by a single, 8-bit, successive ap-
proximation digital to analog converter (DAC). The output of
the DAC is compared with the sampled value by the Com-
parator (Comp).
ADC Control Logic performs a 10 clock cycle successive
approximation algorithm to find the digital representation of
the input signal.
Configuration (Config) automates ADC operation. Four op-
erational modes allow the ADC to convert one or four of the
input signals, in single or repetitive (scan) modes.
The ADC interfaces through the four status and control reg-
isters with the peripheral bus. the four data output buffers
also interface with the same bus, and can store up to four
conversion results.
The Clock Divider reduces the frequency of the system
clock to the lower value required by the ADC. The on-chip
V
DAC reference input.
REF
source can be enabled and connected internally to the
_
+
Comp
Config
ADCCLK
ADC
and Control
Registers
Status
Buffers
Divider
Clock
Data
S
capacitor during the sam-
PC87570
Peripheral
System
Reset
Clock
Bus