ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 5

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

4.0
5.0
3.3
3.4
3.5
3.6
On-Chip Memory
4.1
4.2
Host Bus Interface (HBI)
5.1
5.2
5.3
5.4
5.5
5.6
3.2.3
CLOCK AND BUS CYCLES ...................................................................................................... 34
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
DEVELOPMENT SUPPORT ..................................................................................................... 44
3.4.1
3.4.2
BIU REGISTERS ....................................................................................................................... 45
3.5.1
3.5.2
3.5.3
USAGE HINTS .......................................................................................................................... 46
INTERNAL RAM ........................................................................................................................ 47
INTERNAL ROM ........................................................................................................................ 47
4.2.1
4.2.2
FEATURES ................................................................................................................................ 48
HOST ACCESS TO SHARED MEMORY DEVICE ................................................................... 49
5.2.1
5.2.2
5.2.3
CORE ACCESS TO RTC/APC .................................................................................................. 49
5.3.1
USAGE HINTS .......................................................................................................................... 49
5.4.1
5.4.2
5.4.3
HOST ACCESS TO PC87570 RESIDENT I/O DEVICES ......................................................... 50
5.5.1
5.5.2
5.5.3
KBC CHANNEL ......................................................................................................................... 50
5.6.1
5.6.2
5.6.3
Byte Accessing ............................................................................................................ 34
Clock Cycles ................................................................................................................ 34
Control Signals ............................................................................................................ 35
Early Write Bus Cycle .................................................................................................. 36
Late Write Bus Cycle ................................................................................................... 38
Normal Read Bus Cycle .............................................................................................. 40
Fast Read Bus Cycle ................................................................................................... 42
I/O Expansion Bus Cycles ........................................................................................... 43
I/O Expansion Example ............................................................................................... 44
Bus Status Signals ...................................................................................................... 44
Core Bus Monitoring .................................................................................................... 44
BIU Configuration Register (BCFG) ............................................................................ 45
I/O Zone Configuration Register (IOCFG) ................................................................... 45
Static Zone Configuration Register (SZCFGn) ............................................................ 45
Access Times .............................................................................................................. 47
ROM Shadow .............................................................................................................. 47
Enabling Shared Memory Mode .................................................................................. 49
Memory Device Interface ............................................................................................. 49
Host Access to Shared Memory .................................................................................. 49
Host and CR16A Arbitration over RTC/APC ............................................................... 49
Shared Memory ........................................................................................................... 49
Wake-Up from Host ..................................................................................................... 50
Host Power-on Indication ............................................................................................ 50
Host Access to Configuration Registers ...................................................................... 50
Host Access to Resident I/O Devices .......................................................................... 50
Host Bus I/O Cycles .................................................................................................... 50
Status Register ............................................................................................................ 50
DBBOUT Register ....................................................................................................... 51
DBBIN Register ........................................................................................................... 51
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