ADP315PC87570 National Semiconductor, ADP315PC87570 Datasheet - Page 55

• Manufacturer Part Number: ADP315PC87570
• Description: Keyboard and Power Management Controller
• Manufacturer: National Semiconductor

5.12.1 Control and Status Register 1 (CST1)
The CST1 Register is a byte-wide, read/write register. It al-
lows the CR16A core to control the host and CR16A arbitra-
tor operation. On reset, bits 0, 1 and 2 of are cleared to 0.
Bit 0 - Lock RTC Host Access (LKRTCHA)
Bit 1 - RTC Master Reset (RTCMR)
Bit 2 - RTC Lock Violation (RTCLV)
Bit 3 - Host Power On (HPWRON)
Bit 4 - Host Master Reset Active (HMRA)
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The HBI arbitrates the usage of the RTC between the
host and CR16A. In case of a conflict, the later of the
two transactions is placed on wait by extending it until
the completion of the prior one. The HIOCHRDY signal
is used to extend the host bus transaction.
0: Disables CR16A access to RTCCA and RTCCD
1: Enables CR16A access to the RTCCA and RTCCD
The CR16A firmware may use this bit to override the
RTC CMOS-RAM protections set by the host at the RLR
register located at Bank 2 of the RTC/APC. See Chapter
6, Section 6.6.4. The CR16A firmware can write a 1 to
this bit to generate a reset pulse to the RTC. Since this
reset pulse only affects the RLR register, it will release
the RTC memory protection mechanisms, and will en-
able the CR16A access to the protected memory. If this
feature is used, the CR16A firmware should store the
RLR register value before resetting it and restore its val-
ue before it returns the control of the RTC to the host.
This bit is automatically cleared by the hardware once
the reset pulse is completed. Writing 0 to this bit has no
effect.
RTCLV is set when the host makes an attempt to ac-
cess the RTC while the LKRTC bit is set. Writing 1 to
RTCLV clears it. Writing 0 to RTCLV has no effect.
This bit allows the firmware to monitor the current status of
the HPWRON input pin (Host Power-on). This bit is read
only. Data written to it is ignored.
This bit allows the firmware to monitor the current status of
the HMR input pin (Host Master Reset). This bit is read
only. Data written to it is ignored.
Res
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registers located at core addresses defined in
Table 5-2 on page 54;
Enables host access to the RTC registers located
at host addresses defined in Table 5-4 on page 61,
Registers RTCCSAH/L.
Registers;
Disables host access to RTC registers
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HMRA HPWRON RTCLV RTCMR LKRTCHA
4
3
2
1
Host Bus Interface (HBI)
0
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5.12.2 Control and Status Register 2 (CST2)
The CST2 Register is a byte-wide, read/write register. It al-
lows the CR16A to control configuration register operation
and the APC-OFF event. On reset, bits 0, 1 and 3 are
cleared to 0. During power-up or WATCHDOG reset, bit 2
is also cleared.
Bit 0 - Host Reset Out (HRSTO)
Bit 1 - Valid Host Configuration Address (VHCFGA)
Bit 2 - Host Configuration Address Lock (HCFGLK)
Bit 3 - APC-OFF Event Enable (APCOFFE)
5.12.3 RTC Core Address Register (RTCCA)
The RTCCA Register is a byte-wide, read/write register. A
write to this register writes the RTC Address Register. A
read from this bit reads the RTC Address Register. This reg-
ister should be accessed by the PC87570 firmware, only
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Enables the PC87570 to generate a host soft reset via
firmware, using the HRSTO pin. The pin is held low (re-
set is active) for as long this bit 1. Se also Figure 5-5 on
page 54
0: De-asserts (high) the HRSTO signal (unless reset
1: Asserts (low) the HRSTO output.
This bit is set by a write to the HCFGBAH Register, as
detailed in the update sequence in Section 5.12.5. It
may be cleared by the firmware by writing 1 to it. Writing
0 to it is ignored. This bit can be locked and made read
only, by setting HCFGLK (bit 2 below).
The address in the HCFGBAL and HCFGBAH Regis-
ters is sampled during the first PnP sequence (at the
first write); any subsequent changes to this register are
ignored. See Figure 5-7 on page 59.
1: Address stored in HCFGBAL and HCFGBAH Reg-
0: Address stored in HCFGBAL and HCFGBAH Reg-
HCFGLK is cleared during power-up and WATCHDOG
reset, but is unchanged during warm reset (HMR). Once
written 1, this bit becomes read only, and cannot be
cleared by the firmware.
0: Configuration base address may be changed (i.e.,
1: VHCFGA (bit 1) and HCFGBAL and HCFGBAH
This bit controls the routing of the APC-OFF event to
iCU and MIWU. See also Table 9-2 and Table 10-1.
0: Disables the APC-OFF event so that it cannot inter-
1: Enables the APC-OFF event from the RTC/APC to
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Res
is extended via its other sources).
isters is valid
isters is invalid, and is ignored during the PnP con-
figuration sequence.
writing to VHCFGA (bit 1) and HCFGBAL and
HCFGBAH Registers is enabled).
Registers are locked, and become read only. Data
written to them is ignored.
rupt the PC87570. APC-OFF events that are de-
tected while this bit is cleared are ignored by the
MIWU.
reach the MIWU and ICU.
5
4
APCOFFE HCFGLK VHCFGA HRSTOB
3
2
1
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