AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 10

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Core Differences
Core Differences
conjunction with the TLB arrays, allow the MMU to be set up to provide address translation, access
protection, and attribute generation on a page-by-page basis. The master translation table is user definable
and is maintained and managed by software with no format requirements.
Unlike the AIM PowerPC architecture, the MMU in the e500 is always on and cannot be disabled. During
Reset, all of the TLB entries in the L1 MMU and L2 MMU are invalidated by the hardware and entry 0 of
the TLB1 array is initialized to allow supervisor only access to the last 4K page in the memory map. This
is address range 0xFFFF_F000–0xFFFF_FFFF. This allows access to the reset vector location. The
initialization code that runs after reset configures the other entries of the MMU to allow access to all other
components in a system.
In the following debugger initialization example, you can see that the MAS registers are re-used to configure
different peripherals on the PowerQUICC III. The following code example assumes that the debugger
already knows that CCSRBAR is at the default position (0xFF70_0000) and that the internal SRAM has
been configured to reside at the highest memory position (0xFFFE_0000) in order to cover the default
MMU page (at 0xFFFF_F000–0xFFFF_FFFF).
The configuration, control, and status registers on the PowerQUICC III are all memory mapped and occupy
a 1 Mbyte region of memory. The starting base address of the 1 Mbyte region is programmable using the
CCSR base address register (CCSRBAR). The default base address for the configuration, control, and status
registers is 0xFF70_0000 (CCSRBAR = 0x000F_F700).
The following code sample is an example of an MMU initialization:
#################################################################
# MMU initialization
# First we re-write TLB1 entry 0 using MAS0
writespr 624 0x10000000 # MAS0
# Then we write at 0xFFFFF000 (SRAM) the code to read a TLB entry
writemem.l 0xFFFFF000 0x7C000764 # tlbre
writemem.l 0xFFFFF004 0x7C0004AC # msync
writemem.l 0xFFFFF008 0x48000000 # infinite loop
# Read tlb1 entry 0, execute the code at 0xFFFFF000
writereg PC 0xfffff000
run
sleep 50
stop
# Write at 0xFFFFF000 the necessary code for setting a TLB entry
writemem.l 0xFFFFF000 0x7C0007A4 # tlbwe
writemem.l 0xFFFFF004 0x7C0004AC # msync
writemem.l 0xFFFFF008 0x48000000 # infinite loop
# Re-write tlb entry 0
writereg PC 0xfffff000
run
sleep 50
stop
# OK, TLB0 is now set-up, now we turn to define our peripherals
# define 256MB TLB1 entry 1: 0x00000000 - 0x0FFFFFFF for DDR Memory
writespr 624 0x10010000 # MAS0
writespr 625 0x80000900 # MAS1
writespr 626 0x00000000 # MAS2
writespr 627 0x0000003f # MAS3
# write tlb entry
writereg PC 0xfffff000
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Migrating from PowerQUICC II to PowerQUICC III
MOTOROLA
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