AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 30

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Software Considerations
Software Considerations
Unlike the 603e core on the PowerQUICC II, the e500 core does not have a reset vector. Instead, the e500
core begins its execution at a fixed virtual address in its memory map at location 0xFFFFFFFC which should
be a branch instruction to the beginning address of the page mapped through TLB1. Although the e500 core
begins its execution in virtual mode as opposed to the real mode of the 603e core, the MMUs can still be set
up to provide real mode addressing where the effective address = the physical address.
(Refer back to Section 2.3.5 for information on how this hardware initialized TLB can be set up.
initialization code in this page should set up more valid TLB entries (and pages) so that the program can
actually branch out of this 4-Kbyte page into other pages for booting the operating system. Similarly, the
interrupt vector area and pages that contain the interrupt handlers should be set up so that exceptions can be
handled early).
5.3 Boot Sequencer
On the PowerQUICC III, the boot sequencer is part of the I2C block and is used (before any boot code is
loaded), to change the default values of internal or external registers in any memory mapped address.
However, in most designs, this block is used to pre-program the PowerQUICC III to boot directly from
memory devices such as burstable Flash, DDR or L2 cache (when configured as L2 SRAM). (On the
PowerQUICC II, the processor could only boot devices that were attached to the 60x bus, using chip select
0 (CS0).
This block also contains a programmable clock divider which allows users to vary its speed anywhere from
160 to 32768 CCB cycles. When this block is running in boot sequencer mode (which is determined during
the initialization procedure via the LGPL3/5 inputs), any register in external memory can be modified by
setting the alternate configuration space (ACS) bit and a supplying a register’s memory address which is
then pointed to by the ALTCBAR register. It is possible, by combining the base address in the ALTCBAR
with that of the 20 bits of address offset supplied from the serial ROM to generate a 32-bit address that is
mapped to the target specified in ALTCAR. Thus, by configuring these registers, the boot sequencer has
access to the entire memory map, one 1-Mbyte block at a time.
6 Software Considerations
The e500 core contains some differences when compared with the 603e core used in other PowerPC
embedded devices. These changes are mainly concerned with supervisor mode resources. Users will need
to make small changes to initialization code when moving from the 603e core to the e500 core but their main
application code should not need to be modified. Most of this supervisor related code has already been
addressed by Motorola’s software third parties and often simply re-compiling with an e500 compliant
compiler is all that is required.
The main areas where users will need to make changes are around the exception handling, memory
subsystem and MMU set up differences of the core. Most user mode software written on the 603e core can
run unchanged on the e500. The only differences surround string instructions and APU specific instructions.
Generally, porting code to the new e500 core will not involve a major amount of effort.
One of the main differences in running application code on the e500 core is that string instructions are no
longer supported, namely: Load String word Immediate (lswi), Load String Word Indexed (lswx), Store
String Word Immediate (stswi) and Store String Word indexed (stswx). The operating systems of most of
the third party software vendors for the PowerQUICC III provide trap emulation when a string instruction
is encountered in compiled code which handles this problem for the end user.
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Migrating from PowerQUICC II to PowerQUICC III
MOTOROLA
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