AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 9

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

2.3.5 Memory Management
The e500 core implements a straightforward virtual address space that complies with the Book E MMU
definition, eliminating segment registers and block address translation resources. Book E defines resources
for fixed 4-Kbyte pages and multiple, variable page sizes that can be configured in a single implementation.
TLB management is provided with new instructions and SPRs.
The e500 core contains a two-level MMU structure as shown in Figure 5.
The L1 MMU is maintained automatically by the hardware and is transparent to the software. It consists of
two four-entry fully associative TLB arrays. One array for instruction and another for data. These arrays
support nine page sizes. There are also two 64-entry, 4-way set associative TLB arrays that support fixed
(4 Kbyte) page sizes. As a result, the L1 MMU is structured into two similar MMU blocks, one MMU block
is used for instruction and the other MMU block is for data.
The L2 MMU is programmed by the user. It consists of one 16-entry, fully associative unified TLB array,
TLB1, which supports nine page sizes. This is similar to the BAT registers in the AIM architecture. There
is also a 256-entry, two-way set associative unified TLB array called TLB0 which supports fixed page sizes
(4 Kbytes). This is similar to the page tables in the AIM architecture. A key difference between the MMU
structures of L1 and L2 is that on the L1 MMU, two separate MMU structures are used to implement data
and instruction entries. In the L2 MMU, the MMU is unified and can be shared by both instruction and data
entries.
The TLB0 and TLB1 arrays are managed by software using tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and
mtspr/mfspr instructions along with six special registers [MAS0–MAS4, MAS6]. These MAS registers in
MOTOROLA
e500
L2 MMU Unified
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
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0
6
MAS 0-4,6
Figure 5. e500 Core MMU Structure
0
3
0
3
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L1VSP
L1VSP
L1 Instruction MMU
L1 Data MMU
15
0
Hardware
Hardware
managed
managed
(Variable)
TLB1
63
63
0
0
L1TLB4K
L1TLB4K
255
0
TLB04K
Instruction
physical
address
Attributes
Instruction
real
address
Attributes
managed
OS
User defined
Global table
mapping of
page table
with page
managed
available
Core Differences
External
memory
Memory
format
OS
all
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