AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 18

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
4.2.1.2 Bypass ATMU Mode
The ATMU bypass mode is a feature that applies specifically to the MPC8560 device and the RapidIO
interface. In this mode, the normal address translation mapping unit (ATMU) of the RapidIO is bypassed so
that messages and maintenance transactions can be sent across RapidIO switches and endpoints without any
mapping or translation overhead. In order to do this, the ATMU parameters (priority, transaction type,
targetid, address) normally obtained from the RapidIO ATMU are supplied in bypass mode.
4.2.1.3 External Master Mode
The PowerQUICC III DMA block has the ability to either handle local transactions within the device or
handle external master initiated DMA transfers through it’s interface (I/O) ports. As in the PowerQUICC II
implementation, external handshake pins are used to request a DMA service or indicate an action:
(DMA_DREQ—data request: transfer start or restart from pause), (DMA_DACK—data accolade: DMA
transfer in progress) and (DMA_DDONE—data done: DMA transfer complete). Figure 9 illustrates the
relationship between the external DMA and the external master pause enable pins.
Data transferred between the PowerQUICC III and external masters can be controlled much more
effectively than on the PowerQUICC II due to the new pause mode. As before, the DMA controller on the
PowerQUICC III can operate in continuous mode and will DMA data out to the external master. However,
for external devices with small FIFO’s such as FPGAs the DMA can quickly overload the FIFO and create
overruns. The new pause mode prevents devices with small FIFO’s filling up as the DMA is paused in
between data transfers by setting MR[EMP_EN]=1 and MR[BWC]=<size of burst>.
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Base Address
DDONE
DREQ
DACK
EMP_EN
CLOCK
Transfer Start
Transfer In Progress
Stride Distance
Stride Size
Transfer Done
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
Figure 9. External DMA Transfer with Pause
For More Information On This Product,
Figure 8. DMA Stride Mechanism
Go to: www.freescale.com
Transfer Start
New Base Address
Transfer Pause
Transfer Restart
New Base Address
MOTOROLA