AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 8

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Core Differences
Core Differences
Unlike the AIM version of the PowerPC architecture, where little-endian mode is controlled on a system
basis, Book E allows control of endian mode on a memory page basis. The e500 core also affects true
little-endian mode by byte swapping.
2.3.3 Internal Memory Subsystem
Both Book E and AIM versions of the PowerPC architecture provide separate instruction and data memory
resources. In addition to the internal 32-Kbyte L1 instruction and 32-Kbyte L1 data cache on the e500 core,
the PowerQUICC III has 256 Kbytes of L2 cache, which is often referred to as the memory complex. This
structure is configurable and its function can be switched between SRAM or cache, or a combination of both
SRAM and cache.
Configured as memory-mapped SRAM, the memory complex can either be split into two separate blocks
of 128 Kbytes each, or one large 256 Kbyte SRAM block. In full cache mode, all 256 Kbytes of the memory
complex are used as L2 cache. Finally, in half-SRAM/half-cache mode, 128 Kbytes of memory-mapped
SRAM and 128 Kbytes of cache are created.
The L2 cache is an 8-way, set-associative, write-through, front-side cache that supports locking on either a
line-per-line basis or on the complete block, unlike the PowerQUICC II, where only the entire cache could
be locked or up to a maximum of three ways. Locking cache blocks allows code in specific areas to be
locked so that it is not modified or updated. For example, this feature can be used to store a non-changing,
but often used subroutine, which can be stored in cache and then locked to enable optimal code efficiency.
Both e500 and 603e cores use the same cache control instructions so that data cache coherency instructions
can be used on the PowerQUICC III. The L2 cache on the PowerQUICC III also has hit under miss
capability, parity checking and generation and a feature called cache stashing.
Stashing allows external masters that drive transactions into the chip to force certain data into the L2 cache
to increase performance. For example, an Ethernet routing application where the processor is simply
receiving an IP header, interrogating the recipient address and forwarding the packet back out, without
looking at the actual payload. Stashing, for example, allows the Gigabit Ethernet controller on the
PowerQUICC III to stash a copy of the header into the L2 cache, so that when the cache gets a hit, it retrieves
this information rather than wasting valuable cycles retrieving the information from DDR SDRAM.
2.3.4 Interrupt Handling
Interrupt handling is generally the same as defined in the AIM version of the PowerPC architecture for the
e500, with the following differences:
8
•
•
•
Book E processors use the IVPR and IVORs to set exception vectors individually. They can also be
set to the address offsets defined in the OEA to provide compatibility with AIM processors. See
Section 6.1, “Exception Handling,” for additional information).
Book E defines a new critical interrupt, that provides an extra level of interrupt nesting. The critical
interrupt includes critical and watchdog timer time-out inputs.
The e500 implements the machine check exception differently from the Book E and from the AIM
definition. It defines a Return from Machine Check Interrupt instruction, rfmci, and two machine
check save/restore registers, MCSRR0 and MCSRR1.
Differences between the e500 and the 603e core register sets are described
in the MPC603e and e500 Register Model Comparison (AN2490).
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
MOTOROLA