AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 21

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
design. In doing so, the AC timing requirements can now be accurately optimized on a per-design basis
using a PCB/layout feedback delay loop as shown in Figure 10.
During layout of the final PCB, the layout engineer needs to set the length of this compensation feedback
loop to be the same as clock tree on the chip. Thus, the internal DLL clock will compensate for the external
clock tree delay and be 100% aligned, allowing maximum margin on the AC timing specifications of the
DDR SDRAM. Of course, this allows maximum flexibility as users can create more or less set up and hold
time to suit their end system requirements.
4.4.3 Six Clock Pairs
Normally in traditional clock design, you should not supply more than three input pins with one clock
otherwise the resulting clock may be degraded under loaded conditions. Due to this reason, the DDR
controller supplies six clock pairs for use with DDR memory. (Some degree of external clock buffering
would be additionally required if users decide to deviate beyond this clock design guideline).
4.4.4 Sleep Mode Support for Self Refreshing SDRAM
Another feature on the DDR SDRAM controller is the ability to support sleep mode for self refreshing
SDRAM. This feature is useful if the clocks or power on the chip have to be stopped for some reason. Prior
to shutting down the power to the chip, this mode executes a self refresh command to the DDR SDRAM
which ensures that the DDR remain intact when it wakens up from the clock stop mode. This allows the
DDR SDRAM to gracefully recover from where it was before the power/clocks were stopped.
4.4.5 Dynamic Power Management
This feature allows users to maximize the bandwidth capabilities of the DDR SDRAM by using on-the-fly
power management. When the DDR transaction pipeline begins to empty, the device automatically uses the
clock enable to put the device into power conservation mode. As new DDR transactions arrive, the devices
comes out of power conservation mode and begins pipelining those new transactions for execution.
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Internal Clock
DDR Controller
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
Figure 10. DDR SDRAM DLL Feedback Delay
DLL
For More Information On This Product,
Go to: www.freescale.com
Clock PCB Trace Length ‘L’
CK
DLL_Sync_Out
DLL_Sync_In
L
2
DLL Timing
Loop
CK
DDR SDRAM
DLL
MOTOROLA