AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 28

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Initialization, Reset and Boot Procedures
Initialization, Reset and Boot Procedures
4.10 Enhanced Debug Features
The PowerQUICC III has a number of new debug features which include a built-in performance monitoring
mechanism. The performance monitoring can be split into two distinct functions: the e500 core performance
monitor and the main PowerQUICC III system performance monitor.
The e500 core performance monitor consists of 32-bit counters that can be cascaded to count up to 4 of 89
defined core events, for example, branches, and cache hits/misses. Access to these performance monitor
counters is achieved through two new performance monitoring instructions: mtpmr and mfpmr (move
to/from performance monitoring register).
In the case of the PowerQUICC III system performance monitor, eight 32-bit counters are available for
general system monitoring with up to 64 system events can be counted on any one of these event counters.
An additional 64-bit counter is also available for larger counting cycles. Using these counters, the user can
monitor up to 576 system events. Typical examples of such events can be found in Table 18-10 of the
PowerQUICC III user’s manual, for example, read or writes from DMA/RapidIO/PCI, ECM dispatch
events, dropped/accepted frames etc.
Also, the provision of a configurable CLK_OUT signal allows the user to select whether the platform (CCB)
or main system clock (SYSCLK) is made available on an external pin for further debug. Users can select
this option via the clock out control register (CLKOCR) as detailed in the MPC85xx Users Manual.
5 Initialization, Reset and Boot Procedures
Existing users of the PowerQUICC I and II device will be familiar with the hard reset configuration word
(RSTCONF) which is used to determine the device configuration while PORESET changes from assertion
to negation. On the PowerQUICC III, the POR configuration stage is a little different. In this section, we
will look at the different initialization, reset and boot procedures of the PowerQUICC III.
5.1 POR Configuration
Perhaps the biggest difference between power on reset (POR) between the PowerQUICC II and the
PowerQUICC III is the removal of the bi-directional HRESET and PORESET pins on the PowerQUICC III.
The SRESET pin on the PowerQUICC II, when asserted, is driven by the chip for 512 clock cycles before
it is released and the SRESET flow is exited. On the PowerQUICC III the function of the SRESET pin is
different and when asserted, causes a machine check exception (mcp) assertion to the core and also a reset
to the CPM.
On the PowerQUICC III, when HRESET is asserted, various device functions are enabled by pulling certain
input pins high or low via external pull-up or pull-down resistors, or using configurable tri-state buffers. At
this point it is perhaps worth noting that all logic on the chip is powered by VDD, only the I/O’s reference
G/L/OVDD. (Ideally, VDD and AVDD should be either powered up simultaneously, or before the other chip
power supplies).
Once these configuration inputs have been valid for at least four clock cycles, the HRESET signal is negated
by the core and then the CPM PLL and e500 DLLs begin to lock. After the DLLs have completed locking,
the boot sequencer (if enabled) is released and can load its configuration data. The PowerQUICC III then
enters the ready state and the e500 core indicates this to the external world by the negation of the ASLEEP
signal and assertion of the READY signal. Chapter 4 of the MPC8560 (MPC8540) Users Reference Manual
gives a list of all the relevant configuration pins and the complete reset procedure. Once the
PowerQUICC III has come out of reset and the system DLLs have locked, the boot process can begin as
configured by the configuration information supplied by the user. This can take the form of:
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Migrating from PowerQUICC II to PowerQUICC III
MOTOROLA
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