AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 17

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
actually a cache hit or not. If the access is a cache hit then the speculative read is ignored and then discarded;
otherwise, if the access is a cache miss, the speculative read transaction completes and a couple of extra
clock cycles have been saved.
There are two arbitration mechanisms inside the ECM; the I/O arbiter and the CCB arbiter. An I/O (for
example, OCeaN, CPM or either of the two TSECs) must first compete for an internal ECM grant for the
CCB with each of the other three I/Os. Arbitration can be won through either a higher priority level access
or a lower priority waiting request. Once arbitration is won, the winning bus request must also compete with
the e500 core for CCB ownership (using the same arbitration mechanisms) before the transaction is finally
entered into the transaction queue. The number of posted transactions by the winning controller is set
through the EEBACR[A_STRM_CNT], which by default is set to three. As a result, by limiting the number
of posted transactions, higher priority transactions or lower priority waiting requests can be arbitrated for
the CCB with the minimum of delay.
4.2 DMA Controller
The DMA controller on the PowerQUICC III is a dedicated 4-channel, independent, general-purpose
controller that can be used by both local and remote masters to transfer data between any memory mapped
area of the PowerQUICC III (for example, PCI, Local Bus, or Rio).
The implementation of the DMA controller is again similar to that of the IDMA implementation on the
PowerQUICC II with ‘traditional’ direct/auto buffer, and chaining modes being supported. However the
PowerQUICC III implementation offers additional features as well as off-loading the main CPM from
performing DMA transactions. The result is an efficient, user-configurable solution that can be controlled
either internally using software or externally using its external DMA I/O pins.
4.2.1 DMA Controller Operation Modes
In addition to the direct and chaining modes of operation, the following new features have been
implemented into the hardware DMA block:
4.2.1.1 Extended Mode—Advanced Chaining/Stride Capability
The advanced chaining mode allows the user to set up a series of buffer descriptors all referenced from a
linked list. The DMA controller, using this linked list, can then walk through multiple buffer descriptors,
allowing complex DMA transactions to be performed.
When operating in stride mode, the PowerQUICC III uses the current base address and adds the
user-defined stride distance to determine the next quantity of data to be transferred. The stride size defines
the amount of data to be transferred before jumping to the address of the next block of data. This feature is
important for DMA transfers to and from fixed memory structures, such as buffer descriptors and buffers.
Figure 8illustrates how the stride mechanism operates.
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Extended mode (Stride capability)
Bypass ATMU mode (RapidIO)
External Master mode
Channel Halt/Abort/Continue mode
Destination/Source Address Hold Enable mode
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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