AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 31

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Software Considerations
Software Considerations
6.1 Exception Handling
The e500 core uses interrupt prefixing and offset registers to set each individual exception vectors. When
migrating code to the e500 core from the 603e core, each exception can be set to the same vector offsets as
on 603e to ensure compatibly.
Machine check handlers also need to be re-written as the e500 core uses a new return from machine check
instruction (RFMCI) and the two machine check save and restore registers called MCSRR0 and MCSRR1.
Normally, the machine check interrupt handler routine should be re-written for the e500 core so that it exits
with this new rfmci instruction.
Some special purpose registers (SPRs) for acquiring exception information are also different with most of
this information being combined into the new e500 exception syndrome register (ESR). A machine check
syndrome register (MCSR) is used to log the cause of the machine check, with the ESR being used to
determine the status. Software can easily overcome this by pointing the e500 exception vectors to a different
address from the 603e vector addresses so that each vector can gather the relevant system information before
jumping to the common (e500/603e) code. On the 603e core, the data storage interrupt status register
(DSISR) was used for this function.
Timer exceptions are compatible between the e500 and 603e core except that the decrementer does not count
pass 0 on the e500. The e500 core also has a new decrementer auto reload feature which can be disabled in
order to be compatible with the 603e core.
6.2 e500 ABI
In order to make it easy to link existing 603e (or ‘classic’ PowerPC) object files, an e500 ABI (application
binary interface) has been created and is used by all the leading third parties implementing e500-based tools.
(This new ABI was required since their was no support on the 603e ABI for floating point registers, 64-bit
SPE registers or embedded support). The e500 ABI specifies low-level system information such as stack
usage and calling conventions as well as object file formats, linking, support of standard libraries and
program loading.
6.3 SPE APU—Floating Point Support
The e500 has floating point capability using the SPE (signal processing engine) APU (auxiliary processing
unit). This is an embedded friendly version and makes use of the 64-bit Simple and Multiple Execution
Units as well as the 64-bit Load/Store unit to perform all of the necessary arithmetic manipulations with
single precision. Users should note that the PowerQUICC III implements floating point operation using
general-purpose registers (GPRs) instead of using floating point registers (FPRs) or vector registers (VRs).
Refer back to Figure 2 for detailed information on the e500 core complex.
The SPE APU and SPFP (signal processing floating point) functionality is implemented on the MPC8540,
the MPC8560 and all future derivatives of PowerQUICC III devices. However, these floating point
instructions will not be supported in devices subsequent to PowerQUICC III. It is strongly recommended
that use of these floating point instructions is confined to libraries and device drivers. Basically, when using
SPE floating point instructions, users should not implement them using assembly code instructions to do
this but rather include the libmoto library file. In doing this, customers protect future software legacy by
simply referring to a single file rather than complete code rewriting on devices subsequent to the
PowerQUICC III.
The libmoto library is a series of hand-optimized library files specifically designed to get 'optimal'
performance when running frequently used software routines in different applications. For example, if we
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Migrating from PowerQUICC II to PowerQUICC III
MOTOROLA
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