AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 27

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
A diagram of the PowerQUICC III PIC is shown in Figure 15.
One of the obvious differences between the PowerQUICC II and PowerQUICC III is the inclusion of the
interrupt sources from the new PowerQUICC III modules i.e. TSEC, DMA, DDR SDRAM controller, PCI,
I2C controller, ECM, RapidIO and the performance monitor. A new feature with BookE is the definition of
a new critical interrupt which provides an extra level of interrupt nesting from either the critical input,
watchdog timer, or from machine check sources. (As on the PowerQUICC II HiP7, critical interrupts can
be taken during normal (non-critical) operation or during regular program flow and use their own critical
save and store registers to save state when they are taken).
There are 16 interrupt priority levels (0–15) on the PowerQUICC III with level 15 being the highest priority
and level 0 disables interrupts from a particular source. This is the opposite to what was on the
PowerQUICC II—level 0 was highest priority, level 15 lowest. Additionally, the PowerQUICC III has four
new Inter-Processor interrupts and four message registers that will be used on next generation multi-core
systems.
On future derivatives, the addition of new or multiple cores will be allowed by the PIC enabling it to be fully
configured and able to route interrupts to any individual core. While the concept of interprocessor interrupts
apparently makes little sense in a single-core device, this feature can serve as a doorbell type interrupt
because external bus masters can write to these interrupt/message registers.
27
formance Monitor
DRAM Controller
ll/Level
ge/Fall
I
2
RISC Timers
C Controller
PCI/PCI-X
TC Layers
L2 Cache
Timer1
Timer2
Timer3
Timer4
MCC1
MCC2
SDMA
SCC1
SCC2
SCC3
SCC4
FCC1
FCC2
FCC3
ECM
Figure 15. PowerQUICIII: Programmable Interrupt Controller
SPI
I
2
C
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Controller
Interrupt
CPM
Go to: www.freescale.com
CPM
INT
PIC
Unconditional Debug
Software Watchdog
Normal Interrupt
Critical Interrupt
3
4
4
4
3
4
4
Timer
Event
TSEC1
TSEC2
DMA (4Ch)
RapidIO
Timers
Message Registers
Inter-Processor
IRQ_OUT
UDE MCP
INT
CINT
Core
e500
MOTOROLA