AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 12

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Communications Processor Module (CPM)
Communications Processor Module (CPM)
2.4 Summary of Core Differences
Table 1 shows a summary of the differences between the e500 (HiP7) and 603e cores. It is expected that on
the current HiP7 silicon, the frequency of the PowerQUICC III device is expected to reach a maximum of
1GHz over time. PowerQUICC III system frequencies in the 667–833 MHz range are currently available
and are functional in system designs now. As previously mentioned, PowerQUICC III HiP8 should give a
significant performance enhancement over these tabulated HiP7 figures.
3 Communications Processor Module (CPM)
The CPM of the PowerQUICC III (like the CPM on the PowerQUICC II HiP 7) supports three full-duplex,
fast communications controllers (FCCs), two multi-channel controllers (MCCs), four full-duplex, serial
communications controllers (SCCs), one serial peripheral interface (SPI), and one I
The following sections highlight the CPM differences between the PowerQUICC II HiP7 and the
PowerQUICC III.
Because the PowerQUICC III’s CPM architecture is nearly identical to the PowerQUICC II, customers can
use existing PowerQUICC II microcode on the PowerQUICC III CPM. However, there are differences in
the interrupt handling of the e500. These differences are described in more detail in Section 4.9,
“Programmable Interrupt Controller (PIC)” and Section 6.1, “Exception Handling.”
12
Auxiliary Processing Units
Address Translation
Frequency (MHz):
Core architecture:
I-Cache/D-Cache:
Instruction issue:
Pipeline stages:
Error Detection:
Table 1. Key Characteristic Differences between e500 and 603e Cores
Associatively:
The clock that drives the CPM block on the PowerQUICC III is generated
from the core-complex bus clock (CCB).
Performance
Features
(APUs):
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Not defined by the classic
PowerPC architecture
16 Kbyte/16 Kbyte
4-way set-associative
None
Real address mode,
Block address translation
(BAT),
and Page address translation
570 MIPs at 300 MHz
(Average 1.9 instruction/cycle)
Go to: www.freescale.com
32-bit classic PowerPC
200–300 –> 450-MHz
MPC82xx 603e Core
Dual-issue
NOTE
4
Signal Processing Engine (SPE),
(Average 2.31 instruction/cycle)
Page Address Translation Only
Parity generation & checking
Est. 1850 MIPs at 800 MHz
BTB Lock, Machine Check
Cache Block Lock/Unlock,
32-bit Book E PowerPC
Performance Monitor,
MPC85xx e500 Core
8-way set-associative
4 Kbyte to 256 Mbyte
667–833 –> 1-GHz
Instruction Select,
fixed-size pages)
(More Flexible:
Variable or
Dual-issue
32K/32K
4 kbyte
2
C bus interface.
7
MOTOROLA