AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 24

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
New Features on PowerQUICC III
New Features on PowerQUICC III
2-Kbytes internal FIFO reaches the 1-Kbyte level, an internal panic alarm raises the priority of the TSEC
block to try to avoid an overrun situation. If the FIFO continues to fill then at the 1.5 Kbytes full level, an
emergency panic increases the DMA priority to its maximum and sends a PAUSE frame to allow the data
that has already been received, to be processed before other data is received.
Another useful feature is the ability to contour the behavior of the TSEC with regard to frame interrupts on
both transmitted and received frames. This feature is known as ‘Interrupt Coalescing’ and can be
implemented using either a frame counting or timer threshold method. In the frame counting
implementation, the user can configure interrupt coalescing such that frame interrupts are deliberately
grouped in order to reduce the number of raised interrupts, thereby avoiding interrupts bandwidth
congestion due to frequent consecutive interrupts. Similarly, stale frame interrupts can be avoided using the
timer threshold approach, beyond which frame interrupts not yet raised are forced. This is an important
feature for helping to optimize packet processing of TSEC frames, by the core.
Although the TSEC is a new hardware block, its programming model is still backwards-compatible with the
PowerQUICC II. As in the PowerQUICC II case, the TSEC transfers data into and out off buffers which are
pointed to by buffer descriptors and connection tables. This helps ensure that any legacy software is
retained.
4.7 PCI/PCI-X
The PCI interface on the PowerQUICC III is the same functional block as on the PowerQUICC II and is
version 2.2 compliant, supporting transaction speeds between 16 to 66MHz. As on the PowerQUICC II
device, the PowerQUICC III PCI controller can either use its internal arbiter to control PCI transactions or
an external arbiter. The PowerQUICC III PCI interface can be configured to operate either as an agent or
host or configured as a master or slave PCI device. As a master device, the PowerQUICC III PCI controller
manages both memory and I/O transactions, whereas as configured as a slave device, only memory
transactions are controlled.
In addition to PCI support, the PowerQUICC III has a new feature which implements the PCI-X standard
(version 1.0A) and can support frequencies up to 133MHz. It is perhaps useful to review the standard PCI
bus architecture that is available on both the PowerQUICC II and the PowerQUICC III, before looking at
the actual differences between the PCI and PCI-X interface.
The PCI bus architecture is a hierarchical, multi-master arbitration scheme that uses either 32 or 64-bit
addressing to post transactions onto the PCI bus. Transactions can be either accepted, retried or deferred. In
the later two cases, the master repeats any transaction that needs to be retried and deferred transactions can
be accepted and started by the target whilst the master retries the transaction. Since the PowerQUICC III
has five different pairs of Request/Grant pairs, up to five external PCI masters can be supported. It is also
worth noting that the PCI interface on the PowerQUICC III is a dedicated interface and does not multiplex
its pins with other functional blocks as it did on the PowerQUICC II. The PowerQUICC II Local Bus pins
and PCI were multiplexed and allowed the use of one interface or the other, for example, local bus or PCI,
but not both. This restriction has now been removed on PowerQUICC III.
The performance of the PCI interface is enhanced by the two level round-robin arbitration algorithm used
in the arbiter and through the ability to do mirror and pre-fetched PCI read accesses. Whilst the PCI interface
supports both inbound and outbound data streaming the amount of data that can actually be streamed is
limited by both the depth of pre-fetching and the target disconnect limit of the PCI specification. On the
PowerQUICC III this disconnect will occur after two cache lines (i.e. after 32 bytes). This helps prevent PCI
devices from hogging the bus, thus avoiding system bottlenecks and interface starvation, when operating
high speed interfaces such as RapidIO or Gigabit Ethernet.
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Migrating from PowerQUICC II to PowerQUICC III
MOTOROLA
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