AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 23

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

New Features on PowerQUICC III
New Features on PowerQUICC III
As on the PowerQUICC II (using the 10/100BaseT, FCC-implemented Ethernet controller), the
PowerQUICC III TSEC can support both full and half-duplex modes (although the 1000BaseT
implementation of the TSEC only supports full duplex mode of operation). The reader should also note that
on the PowerQUICC II HiP7 device, the 10/100BaseT Ethernet can be implemented through a reduced MII
interface. Additionally, the TSEC supports a ten bit interface (TBI) which is used to connect to a SERDES
(SERialize/DESerialize) for fibre/optical transceiver applications. An Ethernet feature comparison between
the PowerQUICC II and PowerQUICC III is summarized in the Table 3.
As in the FCC Ethernet controller (100BaseT) on the PowerQUICC II, the TSEC block supports both
internal and external loopback. However, users should note that internal loopback on the PowerQUICC III
is only supported in GMII, MII or TBI modes—no internal loopback is supported when the controller is
configured in RGMII or RTBI mode. Similarly, as on the PowerQUICC II, external loopback is performed
at the interface pins. On the PowerQUICC II, 64-bits were made available for address hash matching, on the
PowerQUICC III TSEC implementation this has been extended to 256 bits, thereby allowing a greater range
of addresses to be decoded.
Due to the high bit rates involved, the TSEC has a number of hidden operational modes that it uses to
internally manage its FIFO’s to help avert either underrun or overrun conditions. Entering internal TSEC
starve mode is an indication that the Tx FIFO is in danger of under-running. When the FIFO nears empty
(within 0.5 Kbytes) the starve state is entered and the ECM automatically increases the priority of the
internal DMA and also that of the TSEC block, in order to avert the underrun. When the FIFO fills back up
to within 1 Kbyte of empty, the starve mode is shutoff. Similarly in the case of frame reception, when the
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Supported Interfaces
10/100 MII
10/100 RMII
1000TBI
10/100/1000 RGMII
1000 RTBI
10/100/1000 GMII
Capabilities
CPM Bandwidth Used?
Out of Sequence Frames
Pause Frame Capability
Jumbo Frame Support
Frame Padding
Polling Frequency
Truncation Capability
Supported Modes
Graceful Rx Stop
Internal FIFOs
Feature
Migrating from PowerQUICC II to PowerQUICC III
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 3. Ethernet Feature Comparison
Go to: www.freescale.com
Yes, Only on HiP7 Devices
Every 256 Ethernet Clocks
No – Uses DPRAM
PowerQUICC
Up to MINFLR
OOS, Pause
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
II
Every 512 Ethernet Clocks
No, Dedicated H/W Block
Yes – 2KB on Board
OOS, Wait & Pause
PowerQUICC
Yes (9.6KB Max)
Up to 64-bytes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
III
MOTOROLA