AN2662 Freescale Semiconductor / Motorola, AN2662 Datasheet - Page 7

• Manufacturer Part Number: AN2662
• Description: Migrating from PowerQUICC II to PowerQUICC III
• Manufacturer: Freescale Semiconductor / Motorola

1
2
3
pmr 128–131 UPMLCas
pmr 256–259 UPMLCbs
0
USPRG0 is a separate physical register from SPRG0.
The 64-bit GPR registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE vector instructions can access the upper word.
These registers are e500-specific and are not part of the Book E architecture.
(upper) GPR0
MOTOROLA
pmr 384 UPMGC0
pmr 0–3
spr 570 MCSRR0
spr 571 MCSRR1
spr 572
spr 573
spr 308
spr 309
spr 310
spr 304
spr 312
spr 313
spr 314
spr 315
spr 316
spr 317
spr 318
spr 319
Performance Monitor Registers
spr 63
spr 26
spr 62
spr 27
spr 58
spr 59
spr 61
General-Purpose Registers
GPR31
31 32
GPR1
GPR2
32
(Read-Only PMRs)
Debug Registers
UPMCs
CSRR0
CSRR1
MCSR
DBCR0
DBCR1
DBCR2
2
MCAR
DEAR
DBSR
SRR0
SRR1
DAC1
DAC2
DVC2
IVPR
IAC1
IAC2
IAC3
IAC4
ESR
(lower)
DV
3
63
3
63
3
3
3
3
3
General-
purpose
registers
Global control register
Counter
registers 0–3
Local control registers
a0–a3
Local control registers
b0–b3
Interrupt vector
prefix
Save/restore
registers 0/1
Critical SRR 0/1
Machine check SRR
0/1
Exception syndrome
register
Machine check
syndrome register
Machine check
address register
Data exception
address register
Debug control
registers 0–2
Debug status register
Instruction address
compare
registers 1–4
Data address
compare
registers 1 and 2
Data value compare
registers 1 and 2
Interrupt Registers
Migrating from PowerQUICC II to PowerQUICC III
Figure 4. e500 Core Programming Model
Freescale Semiconductor, Inc.
For More Information On This Product,
0
MMU Control and Status (Read/Write)
spr 1012 MMUCSR0
MMU Control and Status (Read Only)
spr 1015 MMUCFG
spr 1010
spr 1011
spr 512 SPEFSCR
spr 513
spr 514
spr 517
spr 400
spr 401
spr 415
spr 528
spr 529
spr 530
spr 531
spr 624
spr 625
spr 626
spr 627
spr 628
spr 630
spr 633
spr 634
spr 688 TLB0CFG
spr 689 TLB1CFG
Instruction-Accessible Registers
spr 48
Go to: www.freescale.com
Supervisor-Level Registers
spr 9
spr 8
spr 1
31 32
ACC
User-Level Registers
L1 Cache (Read/Write)
32
L1CSR0
L1CSR1
3
IVOR32
IVOR33
IVOR34
IVOR35
BBEAR
BBTAR
NPIDR
IVOR15
MAS0
MAS1
MAS2
MAS3
MAS4
MAS6
IVOR0
IVOR1
PID1
PID2
PID0
CTR
• • •
XER
CR
LR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
63
63
3
3
3
3
3
3
3
Condition register
Count register
Link register
Integer exception
register
SP/embedded FP
status/control register
Accumulator
Branch buffer entry
address register
Branch buffer target
address register
Nexus processor ID
register
Interrupt vector offset
registers 0–15
Interrupt vector offset
registers 32–35
MMU control and status
register 0
MMU assist registers
0–4 and 6
Process ID
registers 0–2
MMU configuration
TLB configuration 0/1
L1 Cache
Control/Status 0/1
pmr 144–147 PMCa0–3
pmr 272–275 PMCb0–3
0
spr 272–279 SPRG0–7
pmr 16–19
spr 1008
spr 1009
spr 1013
pmr 400
spr 256
spr 259
spr 260
spr 263
Time-Base Registers (Read-Only)
spr 268
spr 269
spr 515
spr 516
spr 286
spr 287
spr 284
spr 285
spr 340
spr 336
Performance Monitor Registers
User General SPR (Read/Write)
spr 22
spr 54
Timer/Decrementer Registers
General SPRs (Read-Only)
Miscellaneous Registers
31 32
Configuration Registers
L1 Cache (read-only)
32
PMC0–3
L1CFG0
L1CFG1
USPRG0
PMGC0
BUCSR
DECAR
SPRG3
SPRG4
SPRG7
HID0
HID1
MSR
• • •
PVR
DEC
TCR
TBU
TBU
TSR
TBL
TBL
PIR
Core Differences
3
3
3
3
63
3
3
63
3
3
3
User SPR
general 0
SPR general registers
3–7
Time base
lower/upper
L1 cache
configuration registers
0–1
Machine state
Processor ID
Processor version
register
Decrementer
Decrementer
auto-reload
Time base lower/
upper
Timer control
Timer status
Hardware
implementation
dependent 0–1
Branch control and
status register
General SPRs 0–7
Global control register
Counter registers 0–3
Local control registers
a0–a3
Local control registers
b0–b3
1
7