MT312 Zarlink Semiconductor, MT312 Datasheet
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... Satellite Channel Decoder Design Manual Part Number: Issue Date: MT312 MT312 August 2003 ...
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... Symbol Rate and Code Rate Search Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 DiSEqC™ Transmit and Receive Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.1 DiSEqC™ transmitting messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.2 DiSEqC™ receiving messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 MT312 software control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 MT312 register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Register usage overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 MT312 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 The configuration register (127 4.3 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 ...
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... Automatic gain control read/write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.1 AGC control register 39 (R/ 9.1.2 AGC_REF Reference Value register 41 (R/ 9.2 Automatic gain control read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.1 Measured signal level at MT312 input register 19 ( 9.2.2 Measured AGC feed back value registers 108 - 110 ( 10.0 MPEG Packet Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1 MPEG clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10 ...
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... Viterbi Reference Byte 4 register 91 (R/ 11.2.40 Viterbi Reference Byte 5 register 92 (R/ 11.2.41 Viterbi Reference Byte 6 register 93 (R/ 11.2.42 Viterbi Maximum Error register 94 (R/ 11.2.43 Byte Align Set up register 95 (R/ 11.2.44 Program Synchronising Byte register 98 (R/ 11.2.45 AFC Frequency Search Threshold register 99 (R/ MT312 5 Zarlink Semiconductor Inc. Design Manual ...
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... Secondary 2-wire bus for tuner control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.5 Examples of 2-wire Bus Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.6 Primary 2-wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.2 Absolute Maximum Ratings 13.3 Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.5 MT312 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.6 Alphabetical Listing of Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.0 MT312 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.1 Read/Write Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.2 Read Only Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 15.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 MT312 6 Zarlink Semiconductor Inc ...
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... Figure 19 - One DiSEqC™ data byte - 0x11 (hex) plus parity bit Figure 20 - DVB Transport Packet Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 21 - BKERR example when ERR_IND is low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 22 - BKERR example when ERR_IND is high Figure 23 - MT312 Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 24 - Primary 2-wire Bus Timing Figure 25 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MT312 ...
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... Table 1 - MT312 register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2 - Register usage overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3 - Symbol Sweep Ranges for General Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 4 - Symbol Sweep Ranges for 90MHz System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5 - Viterbi Code Rate Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 6 - Sigma Delta Clock Decimation Ratio Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 7 - MPEG Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 8 - MOCLK Input Minimum And Maximum Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 9 - Read/write Secondary Register Map ...
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... DVB transmission, the MT312 requires a minimum of five registers to be written. The MT312 provides a monitor of bit error rate after the QPSK module and also after the Viterbi module. For receiver installation, a high speed scan or 'blind search' mode is available. This allows all signals from a given satellite to be evaluated for frequency, symbol rate and convolutional coding scheme ...
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... Application Diagram MT312 Figure 2 - Application schematic 10 Zarlink Semiconductor Inc. Design Manual ...
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... The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB standards. Although not a part of the DVB standard, MT312 allows a roll-off of 0. used with other DVB parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure the signal level fed to the MT312 is set at an optimal value under all reception conditions ...
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... The actual value is four times VIT_ERRPER[23:0]. The count of errors found during this period is loaded by the MT312 into the VIT_ERRCNT_H-M-L trio of registers when the bit count VIT_ERRPER[23:0] is reached. At the same time an interrupt is generated on the IRQ line. Setting the IE_FEC[2] bit in the IE_FEC register enables the interrupt ...
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... VIT_MAXERR[7:0] register and the dish alignment on the satellite. This VIT_MAXERR mode is enabled by setting the FEC_STAT_EN register bit-0. Figure 5 below shows the bit errors rising to the maximum value programmed and triggering a change of state on the STATUS line. MT312 VIT_ERRCNT[23:0] VIT_ERRPER[23:0] ...
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... First-In-First-Out (FIFO) memory in branch 0. The switch is operated at regular byte intervals to insert successively received bytes into successive branches. After 12 bytes have been received, byte 13 is written next to the synchronisation byte in branch 0, etc. In the MT312, this de-interleaving function is realised using on-chip Random Access Memory (RAM). ...
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... The Reed-Solomon decoder can correct up to eight byte errors per packet. If there are more than eight bytes containing errors, the packet is flagged as uncorrectable using the pin BKERR. In the case of DVB the Transport Error Indicator (TEI) bit of the MPEG packet is set setting of TEI is enabled. MT312 Sync word route 17x11 bytes ...
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... The de-scrambler also inverts the sync byte B8hex so that all MPEG output packets have the same sync byte 47hex. Sync byte Sync byte Figure 9 - DVB energy dispersal conceptual diagram MT312 187 bytes ...
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... DiSEqC™ v2.2 specification. This includes high/low band selection, polarisation and dish position. In this mode, the symbol rate in MS/s and Viterbi code rate are the only values needed to start the MT312 searching for the signal. The CDC module maps the high level parameters into the various low level register settings needed to acquire and track the signal ...
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... Symbol Rate and Code Rate Search Mode Where the symbol rate and/or the Viterbi code rate are unknown, the MT312 can be programmed to search for QPSK/BPSK signals. The user should define the range(s) over which the search is required. The MT312 will then locate and track any signal detected. Failure to find a QPSK signal in the specified frequency and specified symbol rate ranges will be indicated by interrupts (see section 7.2 “ ...
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... The MT312 is held in a power saving mode following the hardware reset. After a hardware reset, the MT312 must be taken out of the power save mode by writing a one to the MSB of the CONFIG register (see “The configuration register (127)” on page 21). When MT312 is not being used it can be put back into the power save mode by writing a zero to the MSB of CONFIG ...
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... Initialization sequence MT312 will be in the power save mode after a hardware reset. The first command to be written must be to the CONFIGURATION register at address 127. After loading this register, wait 150µs before writing to the RESET register. During this wait, the tuner can programmed to the required channel frequency via the General Purpose Port (register 20) ...
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... If both DSS_A and DSS_B are set high, the MT312 will search for the code rate in DSS mode. If either of the DSS_A or DSS_B are set high, the symbol rate is automatically set to 20MS/s and SYM_RATE registers (23 & 24) are ignored. The matched filter root-raised-cosine roll-off is set to 0.20 and bit-0 of QPSK_CTRL (26) is ignored. ...
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... Maximum Ratings” on page 80. In general therefore, the V simultaneously with the CV supply RESET ADDR[7:1] Don’t care Osc MT312 supply must never, at any time during power-up, exceed DD supply should be established ahead of Don’t care ~1ms typ. Figure 12 - MT312 Power-up Sequence 22 Zarlink Semiconductor Inc. Design Manual ...
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... Program tuner via GPP in 'pass through mode' open port with Reg (40hex) send TUNER DATA via 2-wire bus. close port with Reg Reset MT312 to default register settings Reg21 = 128 (80hex) Set SYS_CLK = 2*Xtal*PLL_RATIO Set DISEQQC_RATIO (if required) Set AGC_SL (if required) Initialise register: reg (32hex) ...
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... I-Q conversion is carried out or because the I and Q connections are swapped between the I-Q converter and the MT312. If spectral inversion is caused by the receiver front-end, then this must be removed by swapping I and Q (within MT312) before QPSK demodulation, by setting the Q_IQ_SP bit-6 of QPSK control register 26 (R/ ...
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... Channel change sequence with search mode If the signal parameters are unknown possible to instruct the MT312 to find a digital signal and report the parameters found. Registers 23 and 24 are programmed with the expected range(s) and the search mode bit SYM_RATE[bit-15] is set high. A code rate search is forced by programming more than one bit in VIT_MODE (25) register ...
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... The FEC is locked to the signal, when byte align lock in FEC_STATUS[bit- The code rate found can then be read from FEC_STATUS[bits 6-4], see section 8.2.2 “FEC status register 6 (R)” on page 51 for details. Figure 14 - Simple channel change sequence MT312 Program tuner via GPP in 'pass through mode' open port with Reg (40hex) send TUNER DATA via 2-wire bus (5 bytes) ...
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... MT312 Program tuner via GPP in 'pass through mode 'open port with Reg (40hex) send TUNER DATA via 2-wire bus (5 bytes). close port with Reg DISEQC_MODE eg Horizontal with 22kHz on: Reg (41hex) Signal input - symbol rate eg 22.0 MS/s: Reg (16hex) Reg ...
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... MT312 Program tuner via GPP in 'pass through mode' open port with Reg (40hex) send TUNER DATA via 2-wire bus. close port with Reg DISEQC_MODE eg Horizontal with 22kHz on: Reg (41hex) Signal input - Search mode eg for SYS_CLK=60MHz and MS/s range: ...
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... GPP_DIR[1:0] are ignored, bit-2: = Input or output set by GPP_DIR[2] - relating to pin 46. Pin 45 = DATA2, this is a transparent, bi-directional connection to the primary DATA1. Pin 44 = CLK2, this is a transparent, bi-directional connection to the primary CLK1. MT312 Program MONITOR to read symbol rate MON_CTRL Reg 103 = 3 Symbol rate = MONITOR_H_L/1024 MS/s " ...
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... If the location of the wanted channel with respect to the current channel is known and if the synthesiser step size is too large to set the precise frequency of that channel, then the FR_OFF register can be used to take up any residual frequency offset. MT312 bit-5 bit-4 bit-3 bit-2 FR_LIM[6:0] - Freq ...
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... MT312 compensates for this frequency offset before it demodulates the signal. Re-tune only if a substantial part of the QPSK spectrum is affected by the base-band filter which precedes MT312. This will be the case only for symbol rates which are close to the maximum symbol rate supported by the above mentioned filters. ...
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... Figure DiSEqC™ data byte interrupting a continuous 22kHz tone The timing periods of the 16ms before the data byte and 16ms afterwards to the interrupt being asserted are clearly shown. The restoration of the 22kHz after the interrupt is controlled by software. MT312 ERR1 ...
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... For mode 4, there is a 16ms delay before the message bytes, then an interrupt is generated 16ms after the last message byte has been sent (see FEC interrupt register 3 (R)). The requisite number of bytes must be pre-loaded into the DISEQC instruction register 36 (R/W) before this bit is set, see page 34. MT312 bit-6 bit-5 bit-4 ...
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... DISEQC_MODE[5:3] as required. The instruction data bytes are modulated onto the 22kHz signal and output from the DISEQC[0] pin. An interrupt is generated 16ms after all the data bytes have been sent and the MT312 then resets DISEQC_MODE[5:0] to zero, see Figure 18 - “A DiSEqC™ data byte interrupting a continuous 22kHz tone,” on page 32 ...
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... Interrupt enable for bit-0 of DISEQC2_INT STAT register 118. Bits-0 and bit-3 are interrupt enables. These determine whether bits-0 to bit-3 of DISEQC2_INT (register 118, see page 37) have any impact on the pin IRQ 57 of the MT312. Note that buffer overflow interrupt does not have an interrupt enable and hence this cannot be brought out to the IRQ pin ...
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... TONE_EXT_PER Tone Impulse Extended Period. bit-1-0: TONE_EXT_PER 000 7 * DISEQC_RATIO 001 8 * DISEQC_RATIO 010 9 * DISEQC_RATIO 011 10 * DISEQC_RATIO 100 11 * DISEQC_RATIO. 101 12 * DISEQC_RATIO. (default) 110 13 * DISEQC_RATIO. 111 14 * DISEQC_RATIO. B[1-0]: MAX_TONE_PER Maximum Tone Period. bit-1-0: TONE_EXT_PER 00 6.0 * DISEQC_RATIO. (default) 01 6.25 * DISEQC_RATIO. 10 5.75 * DISEQC_RATIO. 11 5.5 * DISEQC_RATIO. MT312 36 Zarlink Semiconductor Inc. Design Manual ...
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... Bit-1 indicates a new message has been received. The end of a message is identified by a silent period of about 6 ms following a byte. The end-of-message interrupt bit makes it easier for the host processor to read DiSEqC™ data from MT312. Instead of reading a byte at a time, it can read the message as a whole. ...
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... For example, if four bytes are received, then eight read operations (with auto-increment bit set to zero) are needed to get all data bytes as well as the parity bits. The number of bytes received is given by bits-3-0 of DISEQC2_STATUS BYTES register 119. MT312 bit-6 bit-5 bit-4 ...
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... MHz operation and the device has not been optimised for operation below 1 MS/s. Therefore for example, (with a 90MHz system clock) to search for all signals with symbol rates from 15 MS MS/s, bits 15, 11, 10 & 9 are all set to ‘1’ and all other to ‘0’. MT312 bit-6 bit-5 bit-4 ...
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... MT312 Bit Symbol Rate Sub Range MS/s 11 SYS_CLK/2 to SYS_CLK/3 10 SYS_CLK/3 to SYS_CLK/4 9 SYS_CLK/4 to SYS_CLK/6 8 SYS_CLK/6 to SYS_CLK/8 7 SYS_CLK/8 to SYS_CLK/12 6 SYS_CLK/12 to SYS_CLK/16 5 SYS_CLK/16 to SYS_CLK/24 4 SYS_CLK/24 to SYS_CLK/32 3 SYS_CLK/32 to SYS_CLK/48 2 SYS_CLK/48 to SYS_CLK/64 1 SYS_CLK/64 to SYS_CLK/96 0 SYS_CLK/96 to SYS_CLK/128 Table 3 - Symbol Sweep Ranges for General Case Bit Symbol Rate Sub Range MS/s ...
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... The Viterbi decoder will search for a signal with the code rates selected by this register. If one code rate is selected, the MT312 will search for a signal with only that code rate. If the code rate is unknown then all bits 5-0 may be set, allowing the MT312 to search for all code rates. ...
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... ADR bit-7 bit-6 bit bit-7-1: Reserved - not used. bit-0: GO High = release reset state to start signal capture, automatically reset to zero. Low = no action. If this register is read, it will return zero. MT312 bit-5 bit-4 bit-3 bit-2 Rsvd Rsvd Rsvd AFC_M bit-4 bit-3 bit-2 bit-1 ...
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... High = Enable QPSK_FR_LOCK indication on interrupt pin. bit-3: High = Enable QPSK_FR_UNLOCK indication on interrupt pin. bit-2: High = Enable QPSK calculation complete indication on interrupt pin. bit-1: High = Enable QPSK_TS_MAX indication on interrupt pin. bit-0: High = Enable QPSK_CS_MAX indication on interrupt pin. MT312 bit-5 bit-4 bit-3 bit-2 bit-1 bit-5 bit-4 bit-3 ...
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... High = QPSK_CS sweep on bit-5: High = QPSK_FR_LOCK bit-4: High = QPSK_TS_AGC_LOCK bit-3: High = QPSK_TS_LOCK bit-2: High = QPSK_CS_LOCK bit-1: High = QPSK_CT_LOCK bit-0: Reserved. Must be set low. MT312 bit-5 bit-4 bit-3 bit-2 bit-1 bit-6 bit-5 bit-4 bit-3 bit-2 QPSK_STAT_EN[7:0] 44 Zarlink Semiconductor Inc. Design Manual ...
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... QPSK waits for the FEC to gain lock is programmable via register 81 (see Section 11.2.31 “FEC Lock Time register 81 (R/W)” on page 71). If the FEC does not achieve lock during this period (very unlikely), then MT312 drops its QPSK CT Lock status and resumes search for another QPSK signal. ...
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... High = QPSK LTV limit Reading an Interrupt register resets that register. Frequency and symbol rate search is carried out as follows. If the symbol rate is known then MT312 will search the specified frequency range for this symbol rate. Once the end of this range has been reached, "QPSK end of frequency range search" ...
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... High = QPSK_LOCK NAME ADR bit-7 bit-6 QPSK STAT L 05 bit-7: High = QPSK Timing sweep on bit-6: High = QPSK Carrier sweep on bit-5-0: Reserved MT312 bit-6 bit-5 bit-4 bit-3 bit-2 QPSK_STATUS[15:8] (high byte) bit-5 bit-4 bit-3 bit-2 QPSK_STATUS[7:0] (low byte) 47 Zarlink Semiconductor Inc. ...
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... The accuracy of this reading is within ±0.25% of the actual symbol rate. Note that the channel with this symbol rate can be subsequently re-acquired without a search by programming the 14 MSBs of the above read-out (discarding the two LSBs) as the 14 LSBs of the 16-bit SYM_RATE register (23,24), see page 39. MT312 bit-6 bit-5 ...
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... High = Enable Viterbi lock indication on interrupt pin. bit-2: High = Enable Viterbi BER monitor period reached indication on interrupt pin. bit-1: High = Enable de-scrambler lock lost indication on interrupt pin. bit-0: High = Enable de-scrambler lock indication on interrupt pin. MT312 bit-5 bit-4 bit-3 bit-2 bit-1 49 Zarlink Semiconductor Inc ...
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... High = Enable programmed synchronisation byte in register 98 (see “Program Synchronising Byte register 98 (R/W)” on page 74). bits1-0: DS_LK[1: Number of bytes for de-scrambler to lose lock. The default register value equivalent to 5 bad sync words. MT312 bit-3 bit-2 DS_lock BA_lock VIT_lock BER_tog R/W bit-6 bit-5 bit-4 ...
Page 51
... Viterbi coding rate bit bit-3: High = De-scrambler lock bit-2: High = Byte align lock bit-1: High = Viterbi lock bit-0: Reserved MT312 bit-5 bit-4 bit-3 bit-2 bit-1 FEC_INT[7:0] Interrupt FEC bit-5 bit-4 bit-3 bit-2 FEC_STATUS[7:0] bit5 bit 4 bits 6-4 Code rate indication ...
Page 52
... Reserved M_SNR[14:0]: These two registers provide a indication of the signal to noise ratio of the channel being received by the MT312. It should not be taken as the absolute value of the SNR. 13312 - M_SNR[14:0] Eb/N0 ~ 683 The equation given only holds for Es/N0 values in the range dB, i.e. Eb/N0 values in the range dB. ...
Page 53
... Rs = symbol rate in Baud CR = Viterbi code rate Blk_size = 1632 bits for DVB and 1096 bits for DSS In denominator, the factor 2 is for QPSK, change for BPSK MT312 bit-6 bit-5 bit-4 bit-3 4 RS_BERCNT[23:0] ...
Page 54
... ADR bit-7 AGC_REF 41 AGC_REF[7:0] Front End AGC reference value. The AGC loop control in MT312 is designed to bring the mean square value of the I signal (or the Q signal) at the ADC output (prior to any digital filtering) to the value set by the AGC_REF register. MT312 bit-6 bit-5 bit-4 ...
Page 55
... ERR_DB[7:0] - Error difference (low byte) AGC[13:0]: These two registers provide a measurement of the AGC error feed back value by the MT312 to the front end. Reading the bytes does NOT reset the value.This measurement can be used to provide an indication of the signal level at the input to the tuner. ...
Page 56
... The range of values for (MOCLK_RATIO + 6) will guarantee operation for MSym/s. However, for a restricted range of symbol rates, higher (MOCLK_RATIO + 6) values may be used with a lower MOCLK frequency. The equation in “Data output timing” on page 61 must be evaluated to ensure successful operation and avoid buffer overflow in the MT312. MT312 MOCLK generation mode 0 Use symbol rate for MOCLK generation ...
Page 57
... MANUAL MOCLK = 1 and DIS_SR = 1. This is the External MPEG Clock mode of operation. The external MOCLK is input on the MICLK pin 14. The clock supplied must be a continuous clock, otherwise the data buffers in the MT312 would overflow and data would be lost. The maximum permitted MICLK frequency is: ...
Page 58
... If the EN_TEI bit is low, the TEI bit will not be changed (but note that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output). MT312 58 Zarlink Semiconductor Inc. ...
Page 59
... Figure 21 above shows lock being lost while ERR_IND is low. The event is divided into five significant periods: 1. Packets being received without errors. 2. Packets being received with errors. 3. Signal too poor for any packets to be received (lost lock). 4. Lock regained but packets still have errors. 5. Packets being received again with no errors. MT312 59 Zarlink Semiconductor Inc. Design Manual ...
Page 60
... Figure 22 above shows lock being lost while ERR_IND is high. The events are similar to the previous figure but BKERR remains low when signal lock is lost. Note: the signal on pin 75 can be inverted by setting the BKERIV bit 6 of OP_CTRL register 96, see page 62. MT312 60 Zarlink Semiconductor Inc. ...
Page 61
... RS = symbol rate in MS/s, e.g. 27.5MS/s for typical ASTRA signals e.g. For DVB ASTRA N N The transport Stream clock rate The time to transmit a packet Time to output 188 bytes The gap between packets The gap as number of byte clocks MT312 = 1 * 204/193 * 8/2 * 4/3 *90E6/27.5E6 = 18 = PLL/N = 90E6/18 = 5E6Hz = 204 * 8/2 * 4/3 *1/RS = 1088/RS = 3.9564E-5 sec = 188/5E6 = 3 ...
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... Figure 23 - MT312 Data Output Timing Diagram Parameter Data output delay (when MCLKINV = 1) 10.5 MPEG Packet Data Output Read/Write Registers 10.5.1 Output data control register 96 (R/W) NAME ADR bit-7 OP_CTRL 96 MANUAL_MOCLK BKERIV MCLKINV EN_TEI BSO bit-7: MANUAL_MOCLK Manual MOCLK mode selection, see register 97 on page 50. ...
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... Timing synchroniser frequency lock detector value when MON_CTRL[3: (see page 48). Timing lock detector value when MON_CTRL[3: (see page 48). Phase lock detector value when MON_CTRL[3: (see page 48). The remaining settings of MON_CTRL[3:0] are either reserved for diagnostic purposes or not used. MT312 Reserved MON_CTRL[3:0] MONITOR_H (123) ...
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... PLD_INLK0 76 PLD_ACC_TIME 77 CS_PLD_MPLEN[3:0] SWEEP_PAR 78 SW_LIM_SC[1:0] Table 9 - Read/write Secondary Register Map MT312 bit-5 bit-4 bit-3 bit-2 AGC_INIT[7:0] Front end AGC initial value AGC_MAX[7:0] Front end AGC maximum value AGC_MIN[7:0] Front end AGC minimum value AGC_PWR_SET[7:0] AGC power initial value SNR_THS_LOW[7:0] SNR estimator low threshold ...
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... QPSK_ST_CT 102 HLD_ST AFC_RS M_SRS NXT_FR FCE_ST QPSK_RESET 104 Reserved QPSK_TST_CT 105 QPSK_TST_ST 106 TEST_MODE 125 Table 9 - Read/write Secondary Register Map (continued) MT312 bit-5 bit-4 bit-3 bit-2 STARTUP_INTERVAL[7:0] LOSSLOCK_TH_SW[3:0] FEC_LOCK_TIME[7:0] LOSSLOCK_TIME[7:0] VIT_ERRPER[7:0] Viterbi error period (low byte) SRCH_CYC[1:0] SEARCH_START[2:0] VIT_REF0[7:0] Viterbi reference byte 0 ...
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... QPSK Miscellaneous register 47 (R/W) QPSK MISC (47) QPSK Reserved, must be set low, MISC[bit-7-0] 11.2.8 SNR_LOW threshold value register 48 (R/W) SNR_THS_LOW (48) SNR THS SNR low threshold value. LOW[7:0] MT312 Default value 59 dec. 3B hex. Default value 255 dec. FF hex. Front End AGC maximum value. Default value 0 dec. 00 hex. ...
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... RATE 3 (55 Carrier Synchronisation sweep rate 3. RATE 3[7:0] 11.2.16 Carrier Synchronisation Sweep Rate 4 register 56 (R/ RATE 4 (56 Carrier Synchronisation sweep rate 4. RATE 4[7:0] MT312 Default value 70 dec. 46 hex. Change to 50 dec. 32 hex. after a full reset. Default value 30 dec. 1E hex. Default value 64 dec. 40 hex. ...
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... ADR bit-7 CS KPROP_H 61 NON SNR CS KROP_L 62 bit-15: NONSNR bit-14-10: CS KP2[4:0] bit-9-5: CS KP14:0] bit-4-0: CS KP04:0] MT312 Default value 124 dec. 7C hex. bit-6 bit-5 bit-4 bit-3 TS KPROPE[11:4] TS KPROPE93:0] TS KINTE[7:0] Timing Synchronisation Proportional path coefficients. Timing Synchronisation Integration path coefficients. bit-6 bit-5 bit-4 bit-3 ...
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... TLD OUTLK TH [7:0]Timing Lock Detect threshold when not in lock. 11.2.23 Timing Lock Detect Threshold in lock register 67 (R/W) TLD INLK TH (67) TLD INLK TH[7:0] Timing Lock Detect threshold when in lock. 11.2.24 Frequency Lock Detect Threshold register 68 FLD TH (68) FLD TH[7:0] Frequency lock detect threshold. MT312 bit- bit- bit- bit KI2[4:0] CS KI1[2:0] CS KI0[4:0] Carrier integer tracking coefficients ...
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... PLD INLK TH2[9:0] bit-9-0: PLD INLK TH1[9:0] 11.2.27 Phase Lock Detect Accumulator Time register 77 (R/W) NAME ADR bit-7 PLD ACC 77 TIME bit-7-4: CS PLDMPLEN[3:0] bit-3-0: LOSSLOCK INT SW[3:0] MT312 bit- bit- bit- bit- bit MX[1:0] PLD OUTLK3[9:4] PLD OUTLK3[3:0] PLD OUTLK2[9:6] PLD OUTLK2[5:0] PLD OUTLK1[7:0] CS Sweep rate number max ...
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... QPSK allows more time for the FEC to lock in the presence of a code rate search. If the FEC does not lock within the allotted number of symbol periods, then the QPSK resets the timing and carrier loops and resumes the search for a QPSK signal. MT312 bit-6 bit-5 ...
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... VIT_SETUP O[1:0] bit-7- [1:0] bit-5-4: SRCH CYC[2:0] bit-3-1: SEARCH START[2:0] Table 10 - Viterbi Code Rate Search Start bit- MT312 Default value 16 dec. 10 hex. Default value 16,777,215 dec. hex. bit-6 bit-5 bit-4 bit-3 SRCH CYC SEARCH START [1:0] Frame (or byte) align time out. ...
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... Viterbi Maximum Error register 94 (R/W) VIT_MAXERR (94) VIT_MAXERR[7:0] Viterbi maximum error. This register controls the frequency of the BER indication audio signal, output on the status pin when the FEC_STAT_EN register bit-0 is set high, see pages 13 and 50. MT312 Default value 128 dec. 80 hex. Default value 20 dec ...
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... bit- bit- bit-5: ACC CK bit-4-0: NUM_PLD INT[4:0] MT312 bit-6 bit-5 bit-4 bit-3 BA MV[1:0] Byte Align FSM mode. Byte Align majority voting. Number of bad sync words to unlock the Byte Align. The default register value equivalent to 7 bad sync words. ...
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... QPSK_TST CT (105) QPSK TEST CTRL[7:0] 11.2.51 QPSK Test State register 106 (R/W) QPSK TEST ST (106) QPSK TEST ST[7:0] 11.2.52 Test Mode register 125 (R/W) TEST MODE (125) TEST MODE[7:0]: MT312 bit-6 bit-5 bit-4 AFC NXT FR FCE ST High = Hold state. High = AFC reset. High = Mixer scan reset. ...
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... RADD: 2-wire Register Address (W) RADD is the 2-wire register address the first byte written after the MT312 2-wire chip address when in write mode. To write to the chip, the microprocessor should send a START condition and the chip address with the write bit set, followed by the register address where subsequent data bytes are to be written ...
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... Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address is not recognised, the MT312 will ignore all activity until a valid chip address is received. The 2-wire bus START command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message to point to a particular read register with a write command, followed immediately with a read data command ...
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... ADDRESS (n) Write/read/write operation with repeated start and auto increment off with IAI set high - MT312 as a slave transmitter. This example uses the GPP_CTRL register where the register address 128 (IAI). Data are first read from the GPP_CTRL register, then following a restart, data are written to the GPP_CTRL register. ...
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... Rise time of both CLK1 and DATA1 signals. Rise time of both CLK1 and DATA1 signals, (100pF to ground) Set-up time for a STOP condition. Note 1: The rise time depends on the external bus pull-up resistor. MT312 Figure 24 - Primary 2-wire Bus Timing Table 11 - Primary 2-wire bus timing 79 Zarlink Semiconductor Inc. ...
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... Voltage on output pins (1.8v rated) Storage temperature Operating ambient temperature Junction temperature Note 1: Stresses exceeding these listed under 'Absolute Ratings' may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. MT312 Symbol Min Typ CVDD 1.62 1.8 ...
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... Output levels VOH 1 mA drive current. Tri-state push pull IIN, QIN, TESTCLK, MDO, MOVAL, MOSTRT, MOCLK, BKERR, DISECQ, STATUS Output levels VOL 1 mA drive current, Pins as Tri-state push pull VOH. MT312 9.99 to 16.00MHz. ±25ppm. ±50ppm. 30pF. <35 Figure 25 - Crystal Oscillator Circuit Symbol CVDD VDD CIDD ...
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... Input levels VIH 3.3V input CMOS Input levels VIH CMOS 5.0V input Input levels VIL CMOS Input leakage Current VIN = 0 and VDD 13.5 MT312 Pinout Description Pin Description Table Pin Name 4,5,6,7, ADDR[7:1] Primary 2-wire bus address defining pins 8,11,12 14 MICLK MPEG clock input used to generate MOCLK. Enabled when both register 96 bit 7 and register 97 bit 7 are set high ...
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... ADC core analogue VDD. All pins must be connected. 30 ADCDVDD ADC core digital VDD. All pins must be connected. 25 ADCFVDD ADC core front end VDD. All pins must be connected. 21 PLLVDD PLL VDD. All pins must be connected. MT312 Description Horizontal/Vertical control 83 Zarlink Semiconductor Inc. Design Manual I/O Note V mA ...
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... ADC core front end VSS. Must be connected to analogue GND. 22 PLLGND PLL VSS. Must be connected to analogue GND. 77,78,79 IIN[5:1] Test bus, all inputs must be connected to VSS. , 80,3 Note 1: 5V tolerant pins with thresholds related to 3.3V. MT312 Description 84 Zarlink Semiconductor Inc. Design Manual I/O Note ...
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... DISEQC1 CLK2/GPP0 44 DISEQC2 /GPP2 NC 29 CVDD 2 CVDD 9 14.0 MT312 Register Map RADD is a virtual register with no address containing the address of the register to be accessed written immediately after the 2-wire write address. NAME ADR bit-7 bit-6 RADD N/A IAI AD6 MT312 PIN FUNCTION ...
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... OP_CTRL 96 MANUAL MOCLK BKERIV MCLKINV EN_TEI FEC_SETUP 97 DIS_SR MON_CTRL 103 ERR_IND DISEQC2_CTRL1 121 DISEQC2_CTRL2 122 MIN_PULS_PER CONFIG 127 312_EN MT312 bit-6 bit-5 bit-4 bit-3 2W_PAS GPP_DIR[2:0] PR_312 FR_QP PR_QP FR_VIT PR_VIT PR_BA HV DISEQC INSTRuction length SR_FMT SYM_RATE[13:8] in MS/s (high byte) SYM_RATE[7:0] in MS/s (low byte) ...
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... LNB_FREQ[7:0] Measured LNB frequency error (low byte) M_SNR[14:8] Measured SNR (high byte) M_SNR[7:0] Measured SNR (low byte) VIT_ERRCNT[7:0] - Viterbi error count (low byte) SIG_LEVEL[7:0] - Signal level at MT312 input AGC[23:16] - Front end AGC (high byte) AGC[15:8] - Front end AGC (middle byte) AGC[7:0] - Front end AGC (low byte) ...
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... References 1. European Digital Video Broadcast Standard, ETS 300 421 December 1994. ETS Secretariat 06921 Sophia Antipolis Cedex France. 2. Digital Satellite Equipment Control (DiSEqC™) EUTELSAT European Telecommunications Satellite Organisation 70, rue Balard - 75502 PARIS Cedex 15 France. MT312 88 Zarlink Semiconductor Inc. Design Manual ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...