MT312 Zarlink Semiconductor, MT312 Datasheet - Page 71

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

11.2.28
bit-7-6:
bit-5-3:
bit-2-0:
11.2.29
STARTUP INTERVAL[7:0]
11.2.30
bit-7-4:
bit-3-0:
11.2.31
FEC LOCK TM (81).
FEC LOCK TM[7:0]
The number of symbol periods which the QPSK allows for the FEC to lock after achieving carrier and timing
synchronisation is given by:
The parameter Search Factor is 1 if there is no code rate search and is 8 if there is a code rate search, i.e. the
QPSK allows more time for the FEC to lock in the presence of a code rate search.
If the FEC does not lock within the allotted number of symbol periods, then the QPSK resets the timing and carrier
loops and resumes the search for a QPSK signal.
SWEEP PAR
STARTUP TIME
LOSSLOCK TH
NAME
NAME
NAME
Sweep PAR register 78 (R/W)
Start up Time register 79 (R/W)
Loss Lock Threshold register 80 (R/W)
FEC Lock Time register 81 (R/W)
ADR
SW LIM SC[1:0]
TS NR SWEEP[2:0]
CS NR SWEEP[2:0]
LOSSLOCK TH SPUR[3:0]
LOSSLOCK TH SW[3:0]
FEC LOCK TM * Search factor * 65536
78
ADR
80
SW LIM SC [1:0]
ADR
79
bit-7
bit-7
LOSSLOCK TH SPUR[3:0]
Default value
bit-
7
bit-6
bit-6
bit-
6
Zarlink Semiconductor Inc.
bit-5
bit-5
TS NR SWEEP[2:0]
MT312
STARTUP INTERVAL[7:0]
bit-
Frequency sweep limit scale.
32 dec.
5
71
bit-4
bit-4
bit-
4
bit-3
bit-
bit-3
3
20 hex.
LOSSLOCK TH SW[3:0]
bit-
bit-2
bit-2
CS NR SWEE{[2:0]
2
bit-
bit-1
1
bit-1
bit-
0
bit-0
bit-0
Design Manual
R/W
R/W
R/W
hex
Def
Def
hex
30
49
hex
Def
21