MT312 Zarlink Semiconductor, MT312 Datasheet - Page 49

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

MON_CTRL[3:0] = 5:
Decimation ratio = MONITOR[15:13]/32.
MON_CTRL[3:0] = 6:
M_FLD[7:0]:
MON_CTRL[3:0] = 7:
M_TLD[15:0]:
MON_CTRL[3:0] = 8:
M_PLD[15:0]:
Other settings of MON_CTRL[3:0] are either reserved for diagnostic purposes or not used.
8.0
8.1
8.1.1
When the bits of this register are set high, they enable an event to generate an interrupt on the pin 57. All interrupts
may be enabled together.
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
IE FEC
NAME
Forward error correction read/write registers
Forward Error Correction
FEC interrupt enable register 31 (R/W)
High = Enable DiSEqC™ indication on interrupt pin.
High = Enable byte align lock lost indication on interrupt pin.
High = Enable byte align lock indication on interrupt pin.
High = Enable Viterbi lock lost indication on interrupt pin.
High = Enable Viterbi lock indication on interrupt pin.
High = Enable Viterbi BER monitor period reached indication on interrupt pin.
High = Enable de-scrambler lock lost indication on interrupt pin.
High = Enable de-scrambler lock indication on interrupt pin.
ADR
31
bit-7
bit-6
the value.
IE FEC[7:0] Interrupt enable FEC
MONITOR_H = MONITOR_L = M_FLD[7:0].
This byte contains a number calculated in the TS_FLD Timing synchroniser
frequency lock detector and is used for frequency lock detection in the manual
programming mode.
MONITOR_H = M_TLD_H and MONITOR_L = M_TLD_L.
Measurement of the Timing lock detector value. Reading the bytes does NOT
reset the value.
MONITOR_H = M_PLD_H and MONITOR_L = M_PLD_L
Measurement of the Phase lock detector value. Reading the bytes does NOT reset
bit-5
bit-4
Zarlink Semiconductor Inc.
bit-3
MT312
49
bit-2
bit-1
bit-0
R/W
hex
Def
00
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