MT312 Zarlink Semiconductor, MT312 Datasheet - Page 38

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

6.3.2
bit-7-5:
bit-4-0:
6.3.3
Odd byte read of register 120:
Even byte read of register 120:
This FIFO contains data bytes and parity bits collected. This can hold a maximum of 8 data bytes, 8 parity bits and
8 parity error bits. The parity error bit is defined as the inverse of the exclusive-OR combination (or modulo-2
addition) of all 9 bits (8 data and 1 parity). This bit will be zero when there is no parity error.
Refer to preceding section for buffer overflow.
The received bytes are read from this location with 2-wire bus auto-increment bit set to zero. The received bytes will
be available in the order received, i.e. the buffer is a First In First Out (FIFO) memory.
Note that two read operations are needed for each byte. The first read operation will give the data byte and the
second will provide the associated parity bit (bit-0) and the parity-error bit (bit-1), the other 6 bits will be zero. For
example, if four bytes are received, then eight read operations (with auto-increment bit set to zero) are needed to
get all data bytes as well as the parity bits.
The number of bytes received is given by bits-3-0 of DISEQC2_STATUS BYTES register 119.
DISEQC2_STAT
DISEQC2_FIFO
DISEQC2_FIFO
NAME
NAME
NAME
DISEQC2 Status Indicators register 119 (R)
DISEQC2 FIFO register 120 (R)
Silent period since last received bit, in multiples of 16 ms.
Bits 4-0 are reset to zero when a bit is received. When this 5-bit number reaches 11 (176ms), the
interrupt bit-3 of DISEQC2_INT register is set. This is saturated at 31. Hence if the total period exceeds
496 ms this counter will continue to indicate 31.
DISEQC2 Finite State Machine State. This is primarily for debugging the device.
ADR
ADR
ADR
120
120
119
bit-7
bit-7
bit-7
bit-6
bit-6
bit-6
bit-5
bit-5
bit-5
Reserved
DISEQC2_STATUS[7:0]
Zarlink Semiconductor Inc.
DISEQC2_FIFO[7:0]
bit-4
bit-4
bit-4
MT312
38
bit-3
bit-3
bit-3
bit-2
bit-2
bit-2
bit-1
Par error
bit-1
bit-1
bit-0
bit-0
Par bit
bit-0
R
R
Def hex
Def hex
R
Design Manual
00
00
Def hex
00