MT312 Zarlink Semiconductor, MT312 Datasheet - Page 32

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

any time, especially immediately after lock, the error from each of these registers can be calculated and added
together. In practice only the two most significant bytes of FREQ_ERR1 are required, so that the net offset can be
calculated as:
Where:
Any frequency error in FREQ_ERR2 transfers to FREQ_ERR1 very rapidly after lock, so that any delay between
reading the two values will cause an error in the calculation. It is therefore recommended that the five bytes above
are read as a block, especially if the 2-wire bus is subject to congestion or other delays.
6.0
6.1
The timing periods of the 16ms before the data byte and 16ms afterwards to the interrupt being asserted are clearly
shown. The restoration of the 22kHz after the interrupt is controlled by software.
Screen printouts of DiSEqC™ waveforms
DiSEqC Control
Figure 18 - A DiSEqC™ data byte interrupting a continuous 22kHz tone
f
ERR1 =
PLL
ERR2 =
Rs
OFF
=
=
=
the frequency offset to be applied to the tuner in MHz
FREQ_ERR1[23:8]
the PLL frequency in MHz
FREQ_ERR2[15:0]
the symbol rate in MS/s calculated from the value in the “Symbol Rate Output
registers 116 - 117 (R)” on page 48
f
O F F
=
–
Zarlink Semiconductor Inc.


ERR1
--------------------------------- -
MT312
65536
32
PLL
+
ERR2
------------------------------ -
262144
Rs


Design Manual