MT312 Zarlink Semiconductor, MT312 Datasheet - Page 87

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

14.2
SYM_RAT_OP_H 116
SYM_RAT_OP_L 117
VIT_ERRCNT_M 12
VIT_ERRCNT_H
VIT_ERRCNT_L
RS_BERCNT_M
DISEQC2_STAT 119
RS_BERCNT_H
DISEQC2_FIFO 120
RS_BERCNT_L
FREQ_ERR1 M
QPSK_STAT_H
FREQ_ERR1 H
FREQ_ERR2 H
FREQ_ERR1 L
FREQ_ERR2 L
DISEQC2_INT
QPSK_INT_M
QPSK STAT L
FEC_STATUS
LNB_FREQ H
QPSK_INT_H
LNB_FREQ L
QPSK_INT_L
MONITOR_H
MONITOR_L
RS_UBC_H
SIG_LEVEL
RS_UBC_L
M_SNR_H
M_SNR_L
FEC_INT
AGC M
AGC H
NAME
AGC L
ID
Read Only Register Map
ADR
109
123
124
126
108
110
112
113
114
115
118
111
00
01
02
03
04
05
06
07
08
09
10
11
13
14
15
16
17
18
19
Reserved
bit-7
RS_BERCNT[15:8] - Reed-Solomon bit errors corrected (middle byte)
RS_BERCNT[23:16] - Reed-Solomon bit errors corrected (high byte)
RS_UBC[15:8] - Reed-Solomon uncorrected block errors (high byte)
RS_UBC[7:0] - Reed-Solomon uncorrected block errors (low byte)
RS_BERCNT[7:0] - Reed-Solomon bit errors corrected (low byte)
FREQ_ERR1[15:8] Input frequency error course (middle byte)
FREQ_ERR1[23:16] Input frequency error course (high byte)
LNB_FREQ[15:8] Measured LNB frequency error (high byte)
FREQ_ERR1[7:0] Input frequency error course (low byte)
FREQ_ERR2[15:8] Input frequency error fine (high byte)
FREQ_ERR2[7:0] Input frequency error fine (low byte)
VIT_ERRCNT[15:8] - Viterbi error count (middle byte)
SYM_RAT_OP[15:8] Symbol Rate Output (high byte)
VIT_ERRCNT[23:16] - Viterbi error count (high byte)
SYM_RAT_OP[7:0] Symbol Rate Output (low byte)
bit-6
VIT_ERRCNT[7:0] - Viterbi error count (low byte)
LNB_FREQ[7:0] Measured LNB frequency error (low byte)
QPSK_INT[15:8] Interrupt QPSK (middle byte)
SIG_LEVEL[7:0] - Signal level at MT312 input
QPSK_INT[23:16] Interrupt QPSK (high byte)
QPSK_INT[7:0] Interrupt QPSK (low byte)
AGC[15:8] - Front end AGC (middle byte)
M_SNR[14:8] Measured SNR (high byte)
AGC[23:16] - Front end AGC (high byte)
M_SNR[7:0] Measured SNR (low byte)
AGC[7:0] - Front end AGC (low byte)
MONITOR[15:8] Monitor (high byte)
MONITOR[7:0] Monitor (low byte)
QPSK_STATUS[15:8] (high byte)
bit-5
QPSK_STATUS[7:0] (low byte)
FEC_INT[7:0] Interrupt FEC
ID[7:0] Chip identification.
Zarlink Semiconductor Inc.
DISEQC2_STATUS[7:0]
DISEQC2_FIFO[7:0]
DISEQC2_INT[7:0]
FEC_STATUS[7:0]
bit-4
MT312
87
bit-3
bit-2
bit-1
bit-0
Design Manual
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