MT312 Zarlink Semiconductor, MT312 Datasheet - Page 41

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

7.1.2
bit-7:
When this bit is set high, the Viterbi decoder will start with the IQ phase defined in V_IQ_SP and the code rate
defined in VIT_MODE[5:0], to establish the correct IQ phase of the incoming signal. When this is established, the
V_IQ_SP bit will be set to that phase indication so that it can be read by software for subsequent re-tuning to the
same channel.
bit-6:
If the transmitted signal is known to be spectrally inverted then set this bit to 1. When AUT_IQ is set high, this bit will
indicate the IQ phase following successful channel acquisition. In manual mode, when AUT_IQ is set low, software
is required to determine the spectrum phase and control this bit externally.
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
The Viterbi decoder will search for a signal with the code rates selected by this register. If one code rate is selected,
the MT312 will search for a signal with only that code rate. If the code rate is unknown then all bits 5-0 may be set,
allowing the MT312 to search for all code rates.
It is also possible to choose the starting point for the code rate search by setting a bit in VIT_SETUP[bit-3:1] register
(86). After searching for a signal with the initial code rate, if no signal is found the search proceeds to the next
higher code rate, see page 72. All selected code rates are searched until a signal is found, irrespective of the start
point. Setting the starting code rate for a search to the most likely value, can speed up a search.
In the DSS mode the code rate is not specified using VIT_MODE register. If either of the two DSS bits of the
Configuration Register (127) are set, then the code rates selected by the VIT_MODE register are ignored. The DSS
code rate selection is carried out as described in section 4.1 “Initialization sequence” on page 20.
The result of the search is reported in the FEC_STAT register (6), see page 51.
VIT_MODE
NAME
Viterbi mode register 25 (R/W)
AUT_IQ
V_IQ_SP
CR_7/8
CR_6/7
CR_5/6
CR_3/4
CR_2/3
CR_1/2
ADR
25
AUT_IQ
bit-7
by the transmitter.
Automatic IQ phase
High = Search for correct IQ phase.
Low = Use IQ phase setting in V_IQ_SP.
Swap I and Q inputs to the Viterbi decoder to overcome spectral inversion caused
High = I-Q swap
Low = No I-Q swap
High = Viterbi code rate 7/8.
High = Viterbi code rate 6/7.
High = Viterbi code rate 5/6.
High = Viterbi code rate 3/4.
High = Viterbi code rate 2/3.
High = Viterbi code rate 1/2.
V_IQ_SP
bit-6
Zarlink Semiconductor Inc.
bit-5
CR_
7/8
MT312
41
bit-4
CR_
6/7
bit-3
CR_
5/6
bit-2
CR_
3/4
bit-1
CR_
2/3
bit-0
CR_
1/2
Design Manual
R/W
Def hex
44