MT312 Zarlink Semiconductor, MT312 Datasheet - Page 75

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

11.2.48
bit-7:
bit-6:
bit-5:
bit-4:
bit-3:
bit-2-0:
11.2.49
bit-7-6:
bit-5:
bit-4:
bit-3:
bit-2:
bit-1:
bit-0:
11.2.50
QPSK_TST CT (105)
QPSK TEST CTRL[7:0]
11.2.51
QPSK TEST ST (106)
QPSK TEST ST[7:0]
11.2.52
TEST MODE (125)
TEST MODE[7:0]:
QPSK ST CT
QPSK RESET
NAME
NAME
QPSK State Control register 102 (R/W)
QPSK Reset register 104 (R/W)
QPSK Test Control register 105 (R/W)
QPSK Test State register 106 (R/W)
Test Mode register 125 (R/W)
ADR
102
ADR
104
HLD ST
AFC RS
M S RS
NXT FR
FCE ST
FORCED ST[2:0]
Reserved Must be set low.
REL QP
PR_QP
PR CS
PR TS
PR FE
PR AGC
HLD ST
bit-
Reserved
bit-7
7
bit-
6
Default value
For factory test purposes only.
Default value
For factory test purposes only.
Default value
This register is for testing purposes only.
AFC RS
bit-6
REL QP
bit-5
Zarlink Semiconductor Inc.
M S RS
bit-5
PR_Q
bit-4
MT312
High = Hold state.
High = AFC reset.
High = Mixer scan reset.
High = Get next frequency.
High = Force state.
Forced state.
High = Release QPSK FSM.
High = Partial reset FSM (applies to QPSK control).
High = Partial reset carrier synchroniser
High = Partial reset timing synchroniser (includes fine AGC).
High = Partial reset front-end logic.
High = Partial reset analogue AGC.
0 dec.
0 dec.
0 dec.
P
75
NXT FR
bit-4
PR CS
bit-3
00 hex.
00 hex.
00 hex.
FCE ST
PR TS
bit-2
bit-3
PR FE
bit-1
bit-
FORCED ST[2:0]
2
bit-
1
PR AGC
bit-0
bit-
Design Manual
0
R/W
R/W
hex
Def
hex
Def
00
00