MT312 Zarlink Semiconductor, MT312 Datasheet - Page 72

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

11.2.32
LOSSLOCK TM (82)
LOSSLOCK TM[7:0]
After the FEC locks it can unlock due to a signal fade or a cycle slip. Then the QPSK allows the following number of
symbol periods for the FEC to regain lock:
If the FEC does not regain lock during this number of symbol periods, then QPSK will re-acquire lock.
11.2.33
VIT ERRPER (83, 84 & 85)
VIT ERRPER
[23:0]
11.2.34
bit-7-6:
bit-5-4:
bit-3-1:
bit-0:
VIT_SETUP
NAME
Loss Lock Time register 82 (R/W)
Viterbi Error Period registers 83 - 85 (R/W)
Viterbi Set up register 86 (R/W)
ADR
LOSSLOCK TM * 262144
Viterbi error period. This is the period over which the Viterbi error count is measured. See
Section 8.2.4 “Viterbi error count at Viterbi input registers 11 - 13 (R)” on page 52.
FR AL TM O [1:0]
SRCH CYC[2:0]
SEARCH START[2:0]
EX F LK
86
bit-7
FR AL TM
O[1:0]
Table 10 - Viterbi Code Rate Search Start
Default value
bit-6
bit-6-4
0
1
2
3
4
5
bit-5
Zarlink Semiconductor Inc.
SRCH CYC
Code rate search start at:
[1:0]
MT312
16 dec.
Default value
Frame (or byte) align time out.
Viterbi BER based search cycles.
Code rate search start, only one code rate may be selected.
Exit false lock.
bit-4
72
1/2
2/3
3/4
5/6
6/7
7/8
bit-3
SEARCH START
10 hex.
16,777,215 dec.FF FF FF hex.
bit-2
[2:0]
bit-1
EX F
bit-0
LK
Design Manual
R/W
hex
Def
34