MT312 Zarlink Semiconductor, MT312 Datasheet - Page 65

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

VIT_ERRPER_H
VIT_ERRPER_M
CSACC_DIF_TH 100
STARTUP_TIME
LOSSLOCK_TH
FEC_LOCK_TM
LOSSLOCK_TM
VIT_ERRPER_L
AFC_SEAR_TH
QPSK_TST_CT
QPSK_TST_ST
VIT_MAXERR
QPSK_LK_CT
QPSK_ST_CT
PROG_SYNC
QPSK_RESET
TEST_MODE
BA_SETUPT
VIT_SETUP
VIT_REF4_
VIT_REF0
VIT_REF1
VIT_REF2
VIT_REF3
VIT_REF5
VIT_REF6
Name
ADR
101
102 HLD_ST AFC_RS M_SRS NXT_FR FCE_ST
104
105
106
125
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
98
99
Table 9 - Read/write Secondary Register Map (continued)
FR_AL_TM_O[1:0]
CS_LLK
bit-7
BA_FSM[1:0]
Reserved
LOSSLOCK_TH_SPUR[3:0]
TS_LLK ACC_CK
bit-6
PROG_SYNC_BYTE[7:0] Enabled by FEC_SETUP [2]
VIT_ERRPER[15:8] Viterbi error period (middle byte)
VIT_ERRPER[23:16] Viterbi error period (high byte)
VIT_ERRPER[7:0] Viterbi error period (low byte)
VIT_MAXERR[7:0] Viterbi max. error bit count
VIT_REF0[7:0] Viterbi reference byte 0
VIT_REF1[7:0] Viterbi reference byte 1
VIT_REF2[7:0] Viterbi reference byte 2
VIT_REF3[7:0] Viterbi reference byte 3
VIT_REF4[7:0] Viterbi reference byte 4
VIT_REF5[7:0] Viterbi reference byte 5
VIT_REF6[7:0] Viterbi reference byte 6
REL_QP PR_QP
SRCH_CYC[1:0]
bit-5
BA_MV_[1:0]
STARTUP_INTERVAL[7:0]
QPSK_TEST_CTRL[7:0]
Zarlink Semiconductor Inc.
LOSSLOCK_TIME[7:0]
FEC_LOCK_TIME[7:0]
QPSK_TEST_TS[7:0]
AFC_SEAR_TH[7:0]
ACC_DIF_TH[7:0]
bit-4
Test mode
MT312
65
PR_CS
bit-3
SEARCH_START[2:0]
NUM_PLD_INT[4:0]
LOSSLOCK_TH_SW[3:0]
PR_TS
bit-2
BA_UNLK[3:0]
FORCED_ST[2:0]
PR_FE PR_AGC R/W 00
bit-1
EX_F_LK R/W 34
bit-0
R/W 30
R/W 21
R/W 20
R/W 10
R/W FF
R/W FF
R/W FF
R/W 80
R/W 14
R/W 0A
R/W 06
R/W 04
R/W 02
R/W 01
R/W FF
R/W D4
R/W 47
R/W 23
R/W 20
R/W 04
R/W 00
R/W 00
R/W 00
R/W 00
Design Manual
Def
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