MT312 Zarlink Semiconductor, MT312 Datasheet - Page 30

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

If bit-6 = 0 then: GPP_DIR[2:0] defines the input/output conditions of the GPP pins and:
If a pin[n] is defined as input then:
Allocation of the GPP[2:0] pins is:
The register default state of 20 hex allows the GPP[2] pin to be used for the 3-wire bus enable line and to be kept
low at all times, except when programming the synthesiser.
When GPP[2] pin is used for DiSEqC™ v2.2 input, the GPP_CTRL register will need to be set to zero after every
full reset to make GPP[2] an input.
5.4.2
bit-7:
FR_LIM[6:0] frequency search range 125kHz steps (MHz/8).
This unsigned 7 bit number represents a search range of +/-0 to +/- 15.875MHz.
Default value 30 (hex) = +/- 6.00MHz.
5.4.3
FR_OFF[7:0] Frequency offset correction value in 31.25kHz steps (MHz/32). This 2's complement 8 bit number
represents an offset from -4MHz to +3.96875MHz. Default value 0.
The frequency search is carried out in the range [(-FR_LIM + FR_OFF), (FR_LIM + FR_OFF)]. The frequency offset
register can be useful in reducing the frequency search during channel hopping, especially with low symbol rates. If
the location of the wanted channel with respect to the current channel is known and if the synthesiser step size is
too large to set the precise frequency of that channel, then the FR_OFF register can be used to take up any
residual frequency offset.
FR_LIM
FR_OFF
NAME
NAME
FR_LIM frequency limit register 37 (R/W)
FR_OFF frequency offset register 38 (R/W)
Reserved.
ADR
ADR
37
38
Reserved
bit-7
bit-7
FR_OFF[7:0] 2’s comp. freq. offset in MHz/32
If a pin[n] is defined as output then:
GPP_PIN[n] high forces GPP[n] pin high
GPP_PIN[n] low forces GPP[n] pin low
GPP[n] pin high sets bit GPP_PIN[n] high
GPP[n] pin low sets bit GPP_PIN[n] low
GPP[2] pin = DiSEqC™ v2.2 input, 3-wire bus enable or can be used for any other
application
GPP[1] pin = DATA2 or 3-wire bus data
GPP[0] pin = CLK2 or 3-wire bus clock
bit-6
bit-6
Must be set low.
bit-5
bit-5
FR_LIM[6:0] - Freq. limit in MHz
bit-4
Zarlink Semiconductor Inc.
bit-4
bit-3
MT312
bit-3
30
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
R/W
R/W
Def hex
00
Def hex
Design Manual
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