MT312 Zarlink Semiconductor, MT312 Datasheet - Page 82

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

DC Electrical Characteristics (continued)
13.5
Pin Description Table
Output level open
drain
Input levels VIH
CMOS
Input levels VIH
Input levels VIL
CMOS
Input leakage Current
4,5,6,7,
8,11,12
Pin
14
16
18
19
23
26
27
28
29
32
33
34
35
38
39
40
Parameter
MT312 Pinout Description
ADDR[7:1]
TESTCLK
QSINGP
ISINGP
TEST1
TEST2
MICLK
Name
QREF
RREF
PLL1
IREF
VRM
XTO
VRB
VRT
XTI
NC
Primary 2-wire bus address defining pins
MPEG clock input used to generate MOCLK. Enabled when
both register 96 bit 7 and register 97 bit 7 are set high. In this
mode, MICLK must be continuous.
Crystal clock input or external reference clock input.
Crystal output. An internal feedback resistor to
included
Phase Locked Loop test output
ADC Voltage top reference level
I channel de-coupling input
I channel input
No connection
ADC Voltage middle reference level
Q channel input
Q channel de-coupling input
ADC Voltage bottom reference level
Bias level
For factory test only. This pin must be connected to VSS in
normal operation
For factory test only. This pin must be connected to VSS in
normal operation
External ADC mode clock.
VIN = 0 and VDD
4 mA drive current.
6 mA drive current.
AGC, DATA1, IRQ,
GPP<2:0>
3.3V input
CMOS 5.0V input
Conditions/Pin
Zarlink Semiconductor Inc.
Description
MT312
82
Symbol
VIH
VIH
VIL
XTI
is
VDD
VDD
Min.
0.7
0.7
I/O
I/O
23
26
O
O
Typ.
I
I
I
I
I
I
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
PECL
Note
0.3VDD
Max.
VIL
0.4
0.6
10
Design Manual
Tri-state
3.3
3.3
3.3
3.3
3.3
5
V
1
Unit
V
V
V
V
V
A
mA
3.3
1